Innovations in semiconductor technology and their applications have long been supported by patent protection.

Moore’s Law will continue to be the norm for CMOS transistor density scales over the next eight to ten years. This will be possible mainly thanks to advances in EUV patterning, and the introduction of new device architectures that will allow logic standard cell scaling.

Moore’s Law can’t be continued without innovation in front-end-of-line (FEOL) device architecture. FinFET devices have become the dominant transistor architecture. Transistor density will follow the Gordon Moore-designed path with the above-mentioned innovations. Two-dimensional materials like tungsten disulfide, (WS2), in the channel promise performance improvement because they allow for more aggressive gate length scaling that Si or SiGe. 2D-based devices have multiple sheets that are stacked and connected from one side. Semi-damascene metallization modules will simultaneously increase resistance and capacitance even in the tightest pitch metal layers. Semi-damascene allows us to increase the aspect ratio (to lower resistance), and use airgaps (to control the capacitance rise) between the lines.

The future system will rely on increasing numbers of heterogeneous integrations leveraging 3D and 2.5D connectivity to address the memory wall, increase functionality in form-factor constrained systems, or improve yields for large chip systems. One example of this is high-bandwidth memories (HBM), which are stacked dynamic random access (DRAM), that connect directly to a CPU or GPU through a short interposer.

3D partitioning on-chip memory at lower levels in the cache hierarchy could be beneficial. What happens to the system level when static random access memory is (SRAM), replaced by magnetic RAM (MRAM)?  The traditional layout would have the CPU located next to the caches in an arranged configuration.

Future chips move the caches from one chip to another, which was stacked using 3D wafer bonding techniques. The signals between caches and the CPU travel much shorter distances so a decrease in latency and speed can be expected. A high-density wafer-to-wafer stacking technology is necessary in order to enable partitioning at deeper levels of the cache hierarchy. Wafer-to-wafer hybrid bonds were demonstrated at 700nm interconnect pitch. We believe that bonding technology advances will allow interconnects of 500nm pitch in the near future.

Heterogeneous integration is enabled by 3D integration technologies such as die-to-die or die-to-Si-interposer stacking using Sn microbumps or die-to-silicon using hybrid Cu bonding.  Because SoCs are becoming more heterogeneous, different functions (logic, memory and I/O interfaces as well as analog and …)) can be performed on different chips. This is because not all SoCs use the same CMOS technology. To optimize design cost and yield, it may be more beneficial to use different process technology for different sub-systems. This evolution could also address the need for greater chip diversity and customization.

NAND storage will scale incrementally without any disruptive architectural changes over the next few years. The most advanced NAND products today have 128 layers of storage capacity. Wafer-to-wafer bonding could allow for additional layers of 3D scaling.

Artificial intelligence and IoT are growing semiconductor technologies.  The semiconductor industry has seen a surge in innovation due to IoT and AI. Future markets will be dominated by manufacturers who are able to meet both the IoT and AI requirements for semiconductor chips.

Additionally, 5G networks are being implemented in tandem with the increasing demand for high-performance computing devices. This new market offers huge opportunities for semiconductor manufacturers, provided that innovation is able to keep pace with consumer demand.

The future is also bright for hardware-assisted AI systems that allow computers to “think” as well as “learn” through artificial intelligence with large neuron networks that require low power consumption, so semiconductor technology must adapt to these new considerations. Instead of prioritizing speed or power, semiconductor producers must focus on efficiency.

Our IP professionals are able to offer counsel and assist clients in a wide range of electronic sectors. They draw on years of experience, thought leadership, advanced educational training, and decades of practical business and engineering knowledge to develop the necessary skills to help clients achieve business goals in a variety of electronics sectors, including:

  • Digital and analog circuits
  • Computer architecture and computer systems
  • Coding, cryptography and compression
  • Data storage
  • Electronic design automation
  • Flexible electronics
  • Architecture and applications for graphics processing units
  • Integrated circuits
  • Applications and e-commerce via the Internet
  • Lighting — Plasma and solid-state
  • Systems, memory circuits and technologies
  • MEMS Manufacturing and applications
  • Mobile communication and computing
  • Materials engineering, nanotechnologies and quantum-effect devices
  • Communications and networking
  • Optoelectronics & photonics
  • Near-field and RF communications
  • Semiconductor structures, processes, devices, lithography, and manufacturing equipment
  • Software
  • 3-D printing

We represent both emerging and mature companies in the technology space. Our focus has always been on innovation. Some of the most significant technological breakthroughs 3D monolithic chips have been patented by our team.

PatentPC is focused on the use of intellectual property to assist electronics clients in achieving their business goals and increasing shareholder value. Our integrated IP model combines the expertise of our team across procurement, defense, and enforcement to optimize all aspects of our clients’ IP strategies.

We understand that success depends on our larger team of both our professionals and our clients. We work closely with the top management of our clients when providing advice on technology patenting and deals. This includes strategic, patent procurement, licensing negotiation, litigation, and other critical stages. This collaboration includes optimizing clients’ IP, including training technical teams and in-house counsel, creating enforcement-ready portfolios, negotiating licensing agreements, performing IP due diligence for investment and acquisition opportunities, and protecting or enforcing their intellectual property rights.