Ken; Weng-Dah (Hsinchu, TW)

The invention provides a semiconductor MP wafer process that includes processing a number of MP wafers within batches or in a lot in a single step. The MP wafers is divided into an MP wafer group-1 and an MP wafer group-2. At least one MP wafer of the MP group-1 is processed using a second process step-1 and at least one of the MP wafers from the MP wafer group 2 is processed by a subsequent step-2 process to create distinct components for devices in the MP wafers of the MP wafer groups-1 and 2, respectively. A minimum of one MP wafer of the MP Wafer Group-1 is processed using a third step-3, and at the very least, one MP wafer of the MP Wafer Group-2 is processed using a third step-4, forming the same device component as the MP WAFERS.

1. Field of the Invention

The invention described hereinafter relates to a semiconductor multiproduct (MP) wafer processing. It is a multi-project, multi-product manufacturing process of semiconductor wafers.

2. Description of Related Art

The NRE of new wafers and mask sets required to make semiconductor devices has grown in complexity, cost and size as semiconductor technology gets more complex. The financial hurdles to design and development of semiconductor IP/Libs, IC prototyping, and small-volume production are prohibitive for fabless IC firms. This is particularly relevant to the next generation of nanometer (nm) technology. One way to reduce NRE costs provided by semiconductor foundry suppliers is to provide multi-project wafers that include a mask-shuttle. With a mask-shuttle multi-project service, the foundry provider can spread the initial NRE cost over many customers without fabs, based on number of shuttle seats they require for IC design prototyping for design prototyping purposes.

IC designs and IP/Lib (macro function units) are sent to a mask-shuttle to verify. This is done using open (i.e. non-proprietary) IP/Library or vendor-specific IP/Library. IC designs are combined into a common maskset , and in a prototyping wafer lot. The semiconductor wafers go through the foundry for semiconductors. The chips, whether packaged or unpackaged, are then returned to foundry’s customers and customers who have supplied their IP/Lib designs or IC functional units to produce the multi-project wafer.

The semiconductor IC industry has seen rapid growth for decades. Technological advances in IC materials, processes and design have resulted in new generations of ICs with each generation having less complex and smaller circuits than the previousgeneration. But, these advancements have increased the complexity of making and processing ICs. The IC sector is maturing, but the different operations necessary to fabricate an IC are performed in different places by different companies or by different companies that specialize in a specific area. For instance, IC foundry processes that utilize a mask shuttle to produce multi-project wafers could be employed by multiple customers.

FIG. FIG. 8 shows an example of a multi-project wafer set which contains several process nodes. The mask set 800 comprises a first layer mask 802, a second layer mask 804, a third layer layer mask 806 and a fifth layer mask 812, a sixth layer mask 814, and a eighth layer mask 820 that comprise a multiple technology node mask (MTM). The mask set 800 also includes a fourth layer mask 808 and 810, as well as a seventh layer mask 816 and 818. The masks 802, 804, 806 eight12, 814, and 820 are single technologynode masks (STM). The mask set MTMs (808 816) and (810, 812) each have a distinct first and a second pattern, each associated with each technology node (for instance 65 nm, 90 nm technology nodes). Fourth layer mask mask 808 as well as the 7th layer mask mask 816 are both STMs. They have the pattern that is first (e.g. 65 nm technology Node ). the fourth layer mask 808, and the seventh layer mask mask 816 are both STMs. They include the first pattern (e.g. 90 nm technology node). The mask set 800 can be utilized to create a device incorporating the first pattern and a device including the second pattern.

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