Software Technology for Method for making a substrate circuitized

Invented by Rabindra N. Das, Michael J. Rowlands, TTM Technologies North America LLC

The TTM Technologies North America LLC invention works as follows

Background for Method for making a substrate circuitized

The laminated “printed circuit boards” (also known as PCBs), the chip carriers and similar products (referred to herein as circuitized substrates) are typically constructed using a lamination process that involves a high-temperature and high-pressure bonding of several layers of dielectric and conductive materials (laminates). The conductive layer, which is typically made of copper or copper alloys, is used to provide electrical connections between various devices on the surface of a substrate. Examples of these devices are integrated circuits (semiconductor chip) and discrete devices such as resistors and inductors. The discrete passive device occupies a high percentage of surface area on the finished substrate. This is not desirable from the perspective of future design due to the increasing demand and need for miniaturization of today’s substrates. To increase the surface area of the substrate (also referred to as “real estate”), there are a number of methods. There have been many attempts to combine multiple functions (e.g. Resistors, capacitors, and similar components can be mounted on a single board. These passive devices can be referred to as integral passive devices, or similar, when they are arranged in this way. This means that all functions are integrated within the single component. These components are still able to utilize board “real estate” despite their external positioning.

In response to these limitations, efforts have been made to embed discrete passive elements within the interior portions of the substrate. These components are then referred as embedded passive components. A resistor or a capacitor that is designed to be placed within a substrate (e.g. between certain layers) may therefore be referred as an embedded passive component or, simply, an embeddable resistor or capacitor. A capacitor of this type provides internal capacitance, while a resistor offers internal resistance. This internal positioning means that such devices do not need to be externally placed on the PCB outer surface.

Some of the documents listed here are U.S. Patents. No. In particular, 6,021,050 describes the internal use resistors for PCBs as passive components. As stated in Ser. No. 11/031,074 (now U.S. Pat. No. No. Here are some examples, both of substrates with embedded components, as described above, and also those that use nanopowders or alternative measures. This does not mean that these documents are part of the prior art for this invention.

In U.S. Patent Application Publication No. 2005/0051360A1, entitled ‘Polymer Thin-Film Resistance Paste, A Resistor Made Of Polymer, And A Method For Their Manufacturing,’ There are formulations, an apparatus and a process for applying polymer thick film resistive pastes with high thixotropic indices to make polymer resistors that have improved tolerances. The squeegee blade is tilted from 10 to 85 degrees to the surface. As the squeegee moves in relation to the printed board, the tilted blade creates a fluid rotating motion within the paste bead. This rotational movement increases the shear stress rate of the polymer thick-film resistive paste in the bead. It results in an effective filling of a resistor-shaped hole without air bubbles.

In U.S. Patent Application Publication No. 2005/0000728A1, entitled ‘Wiring Board Providing A Resistor and Process for Manufacturing The Same,’ There is a wiringboard provided with a resistance. The board comprises of an insulating surface with wiring patterns, first and third electrodes separated by a distance, first resistors (horizontal resistors) on the surface with their respective ends connected to the first electrodes and second electrodes.

In U.S. Patent Application Publication 04/0231758A1, entitled ‘Silver-Coated Powders, Method and Apparatus of Manufacture, Devices Containing Silver Made Therefrom’, There is a description of the use of powders containing silver and the method and apparatus to manufacture silver-containing particles with a high-quality, small size and narrow-sized distribution. The liquid is then used to create an aerosol, which is sent to a furnace where the liquid is vaporized, allowing the formation of desired particles. These are collected in a particle collection. Aerosol generation is the preparation of high-quality aerosols with narrow droplet sizes, tight control over droplet sizes, and a high amount of droplets suitable for commercial uses.

In U.S. Patent Application Publication No. 2003/0146418A1, entitled ‘Resistive film,? A resistive film is described for use in potentiometers. The film comes into contact with an movable wiper. The film contains a thermosetting resin and a polymer resin that has been cured. The film is dispersed with conductive particles of graphite and carbon black. These conductive particles make the resins electrically resistant. The film also contains carbon nano-particles. The nanoparticles improve the resistance to wear of the resistive films and reduce noise when the wiper moves over the film.

In U.S. Pat. No. No. 6,967.138, entitled “Process for Manufacturing A Substrate with Embedded capacitor”,? A process is described for the manufacture of a substrate that has an embedded capacitor. This involves forming a first metal layer, including a lower electrolyte pad, on a base substrate. The substrate base is coated with a dielectric layer using a build-up procedure. The dielectric layer is drilled to reveal the lower electrode pad. A medium material is then injected into the hole. The ground surface of the medium material must be parallel to that of the dielectric layer. On the dielectric layer is a second metal wiring pad with an upper electrode pad. The upper electrode pad covers ground surface of medium material, and is parallel to lower electrode pad to form embedded capacitor.

In U.S. Pat. No. No. The use of nanoparticles from intermetallic alloys like FeA1, Fe3A1, NickelA1, TiA1 or FeCoV is described. These alloys have a variety of applications including structural, magnetic and catalytic. The powders are used to produce structural parts with enhanced mechanical properties. They can also be used to create magnetic parts that have enhanced saturation. “In contrast to bulk FeA1 material which is nonmagnetic, FeA1 nanoparticles have magnetic properties at ambient temperature.

U.S. Pat. No. In 6,740 701, entitled “Resistive film”, a resistive sheet is described for use in potentiometers. The film comes into contact with an movable wiper. The film contains a thermosetting resin and a polymer resin that has been cured. The film is dispersed with conductive particles of graphite and carbon black. These conductive particles make the resins electrically resistant. The film is also dispersed with carbon nano-particles. The nanoparticles improve the resistance to wear of the resistive films and reduce the electrical noise when the wiper moves over the film. A polymer solution can be prepared by mixing 10-20 weight percent. A polymer is mixed with 0-10 wt. Percentage of thermosetting resin, 60-80 wt. Percentage of N-methylpyrrolidone based on the total composition. The polymer and nanoparticles are mixed to create a fine-particle paste. Surfactants and rheological add-ins can be added to the resistive composition at this stage if desired. To get a paste that is suitable for use in position sensors, the particle size range and paste viscosity are monitored. The ball milling time, quantity and particle size are determined by the milling.

In U.S. Pat. No. The patent number 6,704,207 entitled “Devices and Methods for Interstitial components in a Printed circuit Board” was published on March 9, 2004. On 9th April 2004, a printed-circuit board (PCB), which has a first surface and a second surface, is described. A device mounted above the board (e.g. an ASIC chip), is also included. A second layer with third and fourth surfaces is included in the PCB. One of the surfaces may include a recess for holding an interstitial part securely. A lead of the component is coupled to the ‘via’, which electrically connects the PCB layers. Interstitial components can include diodes and transistors as well as resistors, thermocouples and capacitors. The interstitial component in what appears to the preferred embodiment is a resistor of a size similar to a 0402? The resistor is manufactured by Rohm Co. and has a thickness around 0.014″”.

In U.S. Pat. No. No. The patent was issued on Sep. 9, 2003. It describes a method of producing integrated capacitance components to be included within printed circuit board. Hydro-thermally prepared micro-powders are used to create dielectric layers with increased dielectric constants that can easily penetrated by microvias. The method described in the patent involves preparing a slurry of hydro-thermally-prepared nano-powder with solvent. The nano-powder suspension is mixed with a suitable bonding agent, such as polymer, to create a composite mixture that is then formed into a layer of dielectric. “The dielectric layer can be placed on top of a conductive coating prior to curing or, if the dielectric is already cured, conductive layers can be added by lamination, metallization, sputtering, or other processes.

In U.S. Pat. No. No. 6,544,651, entitled “High Dielectric Constant Polymer-Ceramic Composite?” Published Apr. On April 3, 2003, a polymer ceramic composite with high dielectric constants was described. It is formed by polymers that contain a metal catalyst for curing (acacs). A certain percentage of Co III can increase the dielectric constant in a particular epoxy. High dielectric polymers, such as epoxy, are combined with fillers (preferably ceramics) to produce two-phase composites that have high dielectric constants. Dielectric constants were found to be greater than 60 for composites with a ceramic volume loading of 30 to 90% and a high-dielectric polymer base, preferably epoxy. This patent also mentions composites with dielectric constants higher than about 74-150. This patent also mentions embedded capacitors that have capacitance density of at least 25nF/cm.sup.2, preferable at least 35nF/cm.sup.2, and most preferably, 50nF/cm.sup.2.

In U.S. Pat. No. No. In a patent published on February 25, 2003, a parallel capacitance structure is described that can be used to form an internal part of larger circuit boards or similar structures in order to provide capacitance. The capacitor can also be used to connect two electronic components, such as chip carriers, circuit board, or even semiconductor chips, while maintaining desired capacitance levels for each component. The capacitor has at least one internal conductor layer, two additional conductors layers on either side of the internal conductor and an inorganic material (preferably a dielectric such as barium titaniumate on the outer surfaces of the second conductor layers). The capacitor also includes outer conductors on top of the dielectric, forming a parallel capacitance between the added and internal conductive layers, and the outer conductors.

In U.S. Pat. No. No. The method described in Dec. 31,2002 is for forming a resistive layer with a pattern that comes into electrical contact with an electrically conductive layer. The three-layer structure consists of a metal conducting layer, an intermediate material layer that is degradable with a chemical etchant and a layer resistive of sufficient porosity that allows the chemical etchant to seep through and chemically destroy the intermediate material. On the resistive layer, a patterned photo-resist is formed. The resistive layer is exposed so that it can be etched by the intermediate chemical layer. “Then, the portions of the resistive layer that have been damaged are abraded away.

In U.S. Pat. No. In U.S. Patent No. 6,446,317 entitled “Hybrid capacitor and method of fabrication therefore”, issued Sep. 10,2002, a hybrid capacitance associated with an integrated-circuit package is described that provides multiple levels excess off-chip capacitance for die loads. The hybrid capacitor comprises a parallel plate capacitor with low inductance embedded inside the package, electrically connected to another source of off chip capacitance. The parallel plate capacitance is located underneath a die and has a top conductive, bottom conductive, and thin dielectric layer which electrically isolates these layers. A set of self aligned via capacitors or one or more discrete capacitances and/or a parallel plate capacitor can be used as the second source of off chip capacitance. Each self-aligned capacitor is embedded in the package and has both an inner and outer conductor. The outer conductor connects to the other conductive layers. Electrical contacts are used to connect discrete capacitors to the conductive layer surface. “During operation, the conductive layer of the low-inductance parallel plate capacitance provides a grounding plane while the other conductive plane provides the power plane.

In U.S. Pat. No. No. 6,396,387 entitled “Resistors for Electronic Packaging” and issued May 28, 2002, describes thin layer resistors that are formed on an insulating substrate. These resistors can be embedded within a printed circuit board. The patent issued on May 28, 2002 describes thin layer resistors that are formed onto an insulating surface. These resistors can be embedded into a printed circuit. The most common resistive materials consist of homogeneous mixes of dielectrics and metals such as platinum. Even small amounts of dielectric materials mixed with metals can increase resistance. The resistive material should be deposited by combustion chemical vapour deposition (CCVD) on the insulating surface. CCVD is used to achieve a homogenous mixture of metals with zero valence and dielectric materials. Etching away any metal-based material resistor, including those made of noble metals, is a good way to form discrete patches. So, a layer resistive material can be covered with a pattern resist, such as an exposed and developed photos resist, and the exposed portions of underlying layers of resistive materials can be etched away. This patent describes the formation thin layer resistors, including an insulating substrate and discrete patches on a layer resistive materials, as well as conductive material placed in electrical contact at spaced-apart positions on the patches. The conductive material provides electrical connections between the resistive patches and electronic circuitry. These structures of insulating materials, resistive materials, and conductive materials can be formed using selective etching techniques.

In U.S. Pat. No. No. The patent was issued on May 28, 2002 and describes a multilayered substrate with built-in capacitances that are used to reduce high-frequency noise caused by voltage fluctuations. The built-in capacitances are formed using at least one type of dielectric material that has been filled in through holes between the ground plane, and the power plane.

In U.S. Pat. No. No. 6,370,012, entitled “Capacitor laminate for use in a printed circuit board and as an interconnector” Published Apr. In a patent issued on April 9, 2002, a parallel capacitance structure is described that can be used to form an internal part of larger circuit boards or similar structures in order to provide capacitance. The capacitor can also be used to connect two electronic components, such as chip carriers, circuit board, or even semiconductor chips, while maintaining the desired capacitance levels for each component. The capacitor includes an internal conductive layer and two additional conductors layers on either side of the internal conductor. It also contains inorganic material (preferably a dielectric such as barium titaniumate on the outer surfaces of the second conductor layer). The capacitor also includes outer conductors on top of the dielectric, forming a parallel capacitance between the added and internal conductive layers, and the outer conductors.

In U.S. Pat. No. No. 6,242,282, entitled “Circuit Chip Packaging and Fabrication Method”, issued Jun. On Jun. 5, 2001, a packaging method for a microchip is described. It includes providing an interconnect material including insulative materials having a first and second sides, initial metallization patterning on the second-side metallized parts of the side but not the non-metallized second-side portions, a substrate through extending from one of the metallized second-side portions and a via chip extending the first-side to the non-metallized second-side portion. The method includes positioning the chip on the second surface with the chip pad aligned to the chip via. It also involves patterning the connection metallization in the via and on selected portions on the first side to extend from the chip pad to the second-side metallized portion. Around the chip, a “substrate” is molded. Or other dielectric materials.

In U.S. Pat. No. No. On 27th January 2001, a fabric/resin dielectric is described for use in laminate structures and a method of their manufacture. The structure can be used in a chip carrier or printed circuit board substrate. The resin can be an epoxy resin, such as the one used in a wide range of?FR-4′ composites. composites. A resin material based on bismaleimide-triazine (BT) is also acceptable, this patent further adding that more preferably, the resin is a phenolically hardenable resin material as is known in the art, with a glass transition temperature of about 145 degrees Celsius (C.).