Software Technology for Translation Lookaside Buffer Invalidation for merged invalidation requests across power boundaries

Apple Inc. (Cupertino, CA)

A method is disclosed in one embodiment for managing memory. This involves receiving a request to delete one of the entries in a translation-lookaside-buffer (TLB) and then receiving another request for the same. Based on this decision the bundles are then removed.

The disclosed subject matter relates to the field of memory management. More specifically however, without the need of exclusion, the disclosed subject matter pertains to power-aware translation lookaside buffer (TLB) optimization to prevent invalidation.

Computers and other computational devices typically have at minimum one processor that is programmable, which is commonly known as central Processing Unit (CPU). They often also include other programmable processors that are utilized for specialized processing of various types including graphic processing operations, which can be carried out by graphic processing units (GPUs). The GPUs are generally composed of multiple cores or elements that can execute the same instructions on parallel data streams. This is why they are more efficient than general purpose CPUs in processing large amounts of data in parallel. A CPU generally acts as host and hand-offs specialized parallel tasks to the GPUs and other specialized processors, such as the neural engine or processor.

Computer memory is required to allow both the CPU and GPU for them to work. Computer memory is usually as cache (random-access memory) or RAM. It’s utilized to store temporary data as well as instructions for GPU and CPU. To make it easier to manage the memory available, address translation is often used. It is typically utilized to speed up access to memory, provide access to greater amounts of virtual memory than actually exists, and/or allow multiple memory requests (e.g. different processes using the GPU or CPU) to share memory. A memory requestor could send an order for memory using a virtual address as well as an address translation mechanism can convert the virtual address to the physical address of the memory.

One embodiment reveals a method for memory management. The method is based on receiving a request to clear one or more entries from the translation lookaside buffer. Additionally, the method involves receiving another request to the removal of some or all entries of the TLB. This method includes mixing the first and second requests. The method further includes finding out if a processor that is associated with the TLB was switched to inactive mode. The method also involves dropping the first and second requests in accordance with the decision.

In one instance, each of the described methods, and variation thereof, can be implemented as a series of computer executable instructions. Such instructions may use any one or more of the aforementioned programming languages. These instructions can be compiled into programs or engines, and stored in any media which is executable and readable by a computer system or another programable device. In various other instances, these instructions may be implemented by an electronic device, e.g., a device,comprising a memory and at least one processor operatively connected to the memory in which the one or more processors are configured to execute the instructions.

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