Three-dimensional semiconductor devices comprise an stacked structure which includes several layers of conductivity stacked on the top of the substrate. The distance in a first direction from sidewalls for two layers of upper and lower conductive layers is smaller than the distance in the second direction that separates the sidewalls for the lower and upper layer of conductivity. The first and second directions cross each other, creating an area that is that is parallel to the substrate. Vertical channel structures enter the structure of stacked.

1. Field

Examples of the inventive idea pertain to a semiconductor device and more particularly to a three-dimensional memory device including three-dimensionally arranged memory cells, and methods for fabricating the identical.

2. Description of the Related Art

To increase a memory capability using the three-dimensional integrated circuit (3DIC) memory method can be used. 3D-IC is a memory technique which allows you to arrange memory cells three-dimensionally.

A punch-and-plug is one 3D-IC technique. Punch-and-plug technique creates thin layers of multi-layered material onto the substrate and creates plugs that penetrate these thin layers. Through this technique, without an increase in production costs, a three-dimensional memory device can be constructed with more memory capacity.

Examples of the innovative concept could be a three-dimensional (3D), semiconductor device with large memory capacity.

Examples of the inventive concept include a 3D semiconductor device that has a number of stacked structures and smaller pad areas.

In accordance with examples of the inventive concept, a three-dimensional semiconductor device includes a stacked structure including a plurality of conductive layers placed on a substrate an area along a primary direction between sidewalls of the upper layer of conductive material and an lower conductive layer that is less than a distance in a second direction between sidewalls of the upper layer of conductive and lower layer of conductive, the first and second directions intersecting each other, forming a planar parallel to a surface supporting the substrate, as well as vertical channel structures penetrating the stacked structure.

Additional bit lines may be used to connect vertical channel structures with one another, with the bit lines running in the first direction.

The stacked structure could also include insulating layers interposed between the conductive layers. The sidewalls of the conductive layers, and the insulating layers that are exposed in the first direction are parallel to one another.

The widths of the plurality conductor layers in the first direction could be roughly equal.

First pads can be found in the layers of conductive. Each pad is exposed by the sequentially stacking of conductive layers. They are separated from vertical structures in the second direction.

Contact plugs are able to be added to the device.

The conductive layers may include second pads, each of which is exposed by a sequentially stacked conductor layer and being spaced apart from the vertical structures in the first direction.

The size of the pad in the first direction might be smaller than a width of the pad in the second direction.

A distance along a third direction between sidewalls of the upper and lower of the conductive layers may be less than the distance in the second direction between sidewalls of the lower and upper layers of the layer that conducts electricity. the third direction being opposite to the second direction.

The distance between the vertical channel structure and the edge of the stacked structure might be shorter in the first direction than in the second.

According to other example embodiments of the inventive concept the three-dimensional semiconductor device is a first stacked structure on a substrate, the first stacked structure including the first memory region, which is divided by a firstvertical channel structure and the first pad region located adjacent to the first memory area, and a second stacked structure on the first stacked structure and the second stacked structure comprising a second memory region penetrated by a second vertical channelstructure as well as a second pad region close to the second memory region and, in a plan view, the major axes of the initial and second structures intersect each one.

The distance between the initial memory region and an edge of the first pad region could be less in the first direction parallel to the top surface of the substrate, than in a or a third direction which crosses the first direction. Likewise, the distance between the second memory region and an edge of the second pad area could be larger in the first direction, but not in the second.

The distance between first memory region (and the edge) of the first pad area may be smaller in the opposite direction from the second. The distance between the second memory region (and the edge) of the second pad region could be smaller in the opposite direction than in first.

The width of the first stacked structure along the initial direction might be less than the width of the second stacked structure along the first direction, and a width of the first stacked structure in the second direction could be greater than awidth of the second stacked structure along the second direction.

An interlayer insulation layer can be added between the primary pad area and the second structure.

Another embodiment of the inventive idea is a three-dimensional semiconductor device that features the stack structure. The stacked structure comprises amemory regions , and at least one pad space adjacent to a first side. A vertical channel structure is inserted into the memory region. Pads are located on the conductive layer in the pad region.

A conductive layer can have a first sidewall that extends significantly in the first direction, and a secondary sidewall that extends considerably in the second direction. The sides of the first of two layers of conductors stacked sequentially in the multiple are aligned with one another to create a uniform flat plane within the memory region. The flat plane can be found located on a different side than the one that is the first.

The pads and the memory region may be adjacent to each other only along the first direction.

To make a flat plane in the memory area, all the sides of the stacked conductive layers can be aligned one another. The flat plane is situated on a different side from the one on which it is located.

A second stacked arrangement may be added to the first stacking structure. The second stacked structuring could include a channel within the memory area, and pads on conductive layers in the pad region and the major axes of both the first and second structures could cross one another.

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1. Create a list of terms that describe your invention, based on the purpose, composition and usage.

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2. Use these terms to search for relevant Cooperative Patent Classifications at the Classification Text Search Tool. If you’re not able to locate the appropriate classification for your invention, scan through the classification’s class Schemas (class schedules). You may want to consider substituting the terms you use for describing your invention, if you fail to find any results in your Classification Text Search with synonyms like the ones you used in the first step.

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5. This list of patent publications is the best to look at for any similarities with your invention. Pay attention to the specification and claims. You may find additional patents by referring to the patent examiner and applicant.

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