Software – Yehuda Binder, May Patents Ltd

Abstract for “System and Method for Routing-Based Internet Security”

The invention discloses a method and system to improve the security of digital data storage or delivery over the Internet as a message from a sender using one or more hops. The sender splits the message into multiple, overlapping or not-overlapping slices using a slicing method. Each slice is then encapsulated in packets that are sent to an intermediate node at a different relay server according to a delivery plan. Relay servers transmit the slices received to another relay server or to their receiver. After receiving all of the slices in a packet, the receiver reverses the slicing process and combines them. This reconstructs the message.

Background for “System and Method for Routing-Based Internet Security”

The Internet is a worldwide network of interconnected computer networks that uses the Internet Protocol Suite (TCP/IP), which includes Transmission Control Protocol (TCP), and the Internet Protocol(IP) to provide services for billions of users around the world. It’s a network of networks made up of thousands of interconnected networks of all types, including public, private, academic, business, government, and other networks. They are connected by many different electronic and optical networking technologies. The Internet provides a wide range of information resources, including interlinked hypertext documents (WWWW) as well as infrastructure for electronic mail. The Internet backbone is the network of data routes that connect large, strategically connected networks to core routers on the Internet. These data routes are hosted at commercial, government, academic, and other high-capacity networks centers. They also host the Internet exchange points, network access points, and network access points that allow Internet traffic to be interchanged between countries, continents, and across oceans. Traffic exchange between Internet service providers (often Tier 1 network) is done through privately negotiated interconnection agreements. This agreement is governed primarily by the principle “settlement-free peering”.

The Internet and its backbone networks do not rely on central control, coordination facilities or global network policies. Its principal architectural features are the ability to place as few network states as possible and control functions in the network elements. Instead, it relies on the endpoints to process most of the processing and ensure data integrity, reliability, and authentication. The high level of redundancy in today’s network links, as well as sophisticated real-time routing protocols, provide alternative routes of communication for load balancing or congestion avoidance.

“The Internet Protocol is responsible to address hosts and route datagrams (packets), from a destination host to a source host across one or more IP network. The Internet Protocol defines two functions for addressing systems. The addresses are used to identify hosts and provide a location service. Each packet is marked with a header that includes the meta-data necessary for delivery. Encapsulation is another name for this process. IP is a connectionless protocol that can be used in a packet switched Link Layer network. It does not require circuit setup before transmission. An upper transport layer protocol addresses the issues of delivery guaranteeing and proper sequencing. It also avoids duplicate delivery and data integrity.

“The Internet protocol design principles assume that the network infrastructure is not inherently reliable at any one network element or transmission medium, and that it is dynamic in terms the availability of links and other nodes. There is no central monitoring or performance measurement facility that monitors or maintains the network’s state. End-to-end principles are used to reduce network complexity. The intelligence of the network is primarily located at the ends of every data transmission. The transmission path routers simply forward packets to next known local gateway matching the routing prefix for destination address.

“The two main components of IP technology are routing and IP addressing. Addressing is how IP hosts are assigned IP addresses. It also describes how sub-networks of IP host address addresses are divided up and grouped together. All hosts perform IP routing, but internetwork routers are the most important. They use either Interior Gateway Protocols or External Gateway Protocols to make IP datagram forwarding decisions across IP-connected networks. Core routers that are part of the Internet backbone use the Border Gateway Protocol, (BGP), as per RFC4098 or Multi-Protocol Label Switching. The following chapters of publication 1-587005-001-3, published by Cisco Systems Inc. in July 1999 and titled “Internetworking Technologies Handbook?”, are included for all purposes. Chapter 5: “Routing basics?” (pages 5-1 through 5-10), Chapter 30,?Internet Protocols? (pages 5-1 to 5-10), Chapter 30:?Internet Protocols? Pages 32-1 to 32-6, Chapter 45: ‘OSI Routing? (pages 45-1 through 45-8) and Chapter 51 :?Security?” (pages 51-1 through 51-12), and IBM Corporation, International Technical Support Organization Redbook documents No. GG24-4756 00 is titled: “Local Area Network Concepts and Products: Management and LAN Operation Systems?, 1st edition May 1996, Redbook document No. GG24-4338 00 is titled: “Introduction To Networking Technologies?”, 1st edition April 1994, Redbook document No. GG24-2580-01 “IP Network Design Guide?”, 2nd Edition June 1999 and Redbook Document No. GG24-3376-01?IP Network Design Guide?, 2nd Edition June 1999 and Redbook Document No.

“A Wireless Mesh Network or WMN (or Wireless Distribution Systems) is a communication system that consists of clients, routers, and gateways connected by radio. These wireless networks can be built on DSR routing protocols. WMNs can be described in a slide show by W. Steven Conner of Intel Corp. titled: ?IEEE 802.11s Tutorial? Presented at the IEEE 802 Plenary in Dallas on November 13, 2006. Slide-show by Eugen Boroci from University Politehnica Bucharest. Titled:?Wireless Mesh Networks Technologies – Architectures, Protocols and Resource Management and Applications?. Also presented in INFOWARE 2009 in Cannes, France. Paper by Joseph D. Camp and Edward W. Knightly, Electrical and Computer Engineering, Rice University in Houston, Texas, USA. All of these papers are incorporated herein for all purposes. This arrangement can also be applied to wireless networks where two clients exchange information via different paths using mesh routers that act as intermediary and relay servers. The routing algorithm in wireless networks is based on MAC addresses. The above discussion on IP addresses is applicable in wireless networks. They use MAC addresses to identify the client initiating the message, as well as mesh routers or gateways serving as relay servers and clients serving as the ultimate destination computers.

FIG. 1a shows a schematic view of an internet-based network 10. 1a . 1a. Various endpoint devices (?hosts?) Different endpoint devices (?hosts?) are shown interconnected via Internet 11. The Internet backbone 11 includes routers 15a-j connected by different bi-directional packet-based communications links 16a-n. The communication links 16a connect routers 15, h, and 15, j. Communication link 16, b connects to routers15 f or 15.j. Communication link 16c connects routings15 h, 15.g, and 16.f. Communication link16 f connects routes15 c and 15.f. Communication link16 g connects Routers15 i and 15.j. Communication link16 k connects to routers15 e. and15 e.a., while communication connection 16 n is used by routers15 a and15 a. Communication link 17a connects laptop12b to the Internet via router15a. Communication link 17b connects router14a to router15 i. Communication link 17c connects router13a to router15 d. Communication link 17d connects router14a to router15 i. Communication link 17e connects router15 i to computer13b. Communication link 17f connects router15 j to computer13 a. Communication link 17g connects router15 g to server14 c, and communication connection 17 i to computer13a to controller15 i to 15 a.

FIG. 1b shows an overview of an IP-based packet 18. 1b . 1b

“The Internet is a packet switching network where packets are sent from their source to their destination through routers. FIG. 20 shows one example of system 20. 2. Laptop 12 a (source?) 2, when laptop 12 a (?source?) wishes to send information desktop computer 13c (?destination?) A packet is created at the source and includes both the destination IP address as well as the source IP address. Different policies and routing algorithms determine how packets are routed over the Internet. The packet is sent first to router 15 j via link 17 g. This schematically can be seen by the dashed line, path 21 a. The packet is sent to router 15, j over link 16, a (designated path 21 b). This forwards it to router 15, h over link 16, a, which then sends it to router 15, g over 16 d (path 21, c). The packet is sent to router 15, g over link 16, e (designated path 21 d). The packet is then forwarded to router 15, f over link 16, k (designated path 21 d). This in turn forwards it to router 15, d over 16 i (path 21, g). The packet is terminated at destination 13 c via the link 17 c. (path 21 h).

“The Internet structure uses a client-server model. The terms “server” and “server computer” are interchangeable. Server? This term refers to a device, computer, or a series thereof that is connected to the Internet. It can be used to provide specific facilities or services for other computers or devices (referred to here as?clients?). Internet. A server is a host with an IP address that executes a “server program” and usually acts as a socket receiver. Many servers offer dedicated functionality, such as web server, Domain Name System server (described RFC 1034/RFC 1035), Dynamic Host Configuration Protocol (DHCP), server (described RFC 2131/RFC 3315), mail server and File Transfer Protocol (FTP), server and database server. The term “client” is also used. The term?client? refers to a program, a device, a computer or series of computers that execute this program. It accesses an Internet server for a service or resource. Commonly, clients initiate connections that may be accepted by a server. Web browsers, for example, are clients that connect with web servers to retrieve web pages. Email clients connect to mail storage server to retrieve mails.

“Network routing is a common term used in the Internet. The network routing devices have the knowledge of the network layout and determine where to forward the packet. In this case, the source only needs to provide the destination IP address. Source routing, a method described by RFC 1940, can be used to determine the path that a packet should follow through the network. Source routing is the method by which a packet travels through the Internet. The sender decides which network route packets should take. Source routing is used. Loose Source Record Route is an alternative form of source routing. The LSRR requires that the sender specifies one or more hops (such an intermediate router) for the packet to pass. Dynamic Source Routing is an efficient and simple on-demand routing protocol that can be used in multi-hop wireless networks of mobile devices such as wireless mesh networks. RFC 4728 describes the DSR. It is intended to reduce the bandwidth used by control packets in ad-hoc wireless networks by eliminating periodic table-update messages, which are required in the table driven approach.

The Internet is a public network that relies on well-known network protocols like TCP/IP. These specifications are widely available and publicly published. A third party (an attacker) can intercept, alter, tamper with or interpret any clear text packets that are being transmitted over the Internet. A third party (?attacker?) may intercept, alter, tamper and interpret any text packets that are sent over the Internet. This makes the Internet unsecure. There are many ways to attack data over the Internet, including network packet sniffers and IP spoofing. It is important to protect sensitive or confidential information that is transmitted over the Internet. This includes bank account details, credit card numbers, criminal records, driver information, vehicle information, loan applications, stock trading, voter information, and any other information. These data are not typically sent as clear text, but encrypted. This means that data is transmitted over the Internet as unreadable data, usually by using a mathematical algorithm.

“Encryption-based mechanisms are typically end-to-end processes that only involve the sender or the receiver. The sender encrypts plain text messages by using an algorithm to transform them. This makes it unreadable to anyone except those with special knowledge. Once the data has been encrypted, it is sent over a network to the receiver. The receiver’s special knowledge allows them to reverse the process and decrypt the message to make it readable. The encryption process commonly involves computing resources such as processing power, storage space and requires time for executing the encryption/decryption algorithm, which may delay the delivery of the message.”

“Transport Layer Security” (TLS) is a non-limiting example of an end-to-end encryption protocol that provides secure communication above the OSI Transport Layer. It uses keyed message authentication codes and symmetric cryptography. TLS clients and servers establish a stateful connection using a handshake process. Various parameters are set during this procedure. This allows for communication that is secure and prevents eavesdropping. RFC 5246 defines TLS 1.2. There are many versions of this protocol in use in web browsing, instant messaging, Internet faxing and voice-over-IP (VoIP) applications. TLS is often used in application design to overlay any of the Transport Layer protocol protocols. This encapsulates the specific protocols of each application, such as HTTP, FTP and SMTP. It has traditionally been used with reliable transport protocols like the Transmission Control Protocol (TCP). It can also be used with datagram-oriented protocols such as the Transmission Control Protocol (TCP) or the Datagram Congestion Control Protocol Protocol (DCCP), which have been standardized using the Datagram Transport Layer Security term (DTLS). TLS is used to secure the World Wide Web traffic that is transmitted via HTTPS. Electronic commerce and asset management are two of the most prominent applications. TLS (RFC 31207) has been increasingly used to protect the Simple Mail Transfer Protocol (SMTP). These applications use public keys certificates to verify endpoint identity. Layer 4 (Transport Layer), and higher layers encryption-based communication protocols are SSH (Secure Shell), and SSL (Secure Socket Layer).

Layer 3 (Network Layer), and lower layer encryption-based protocols include IPsec and L2TP (Layer 2 Tunneling Protocol) both over IPsec and Ethernet over IPsec. IPsec is a protocol suite that encrypts and authenticates each IP packet in a communication session to secure IP communication. RFC 4301 and RFC4309 are the current IPsec standards. It was first described in RFCs 825-1829. Cisco Systems, Inc. has provided an overview of IPsec in the document titled “An Introduction to IP Security(IPSec) encryption?”. This document is incorporated into its entirety for all purposes.

U.S. Pat. explains that there are two common approaches to cryptography. No. No. No. No. The Ehrsam patent describes what is known as Data Encryption Standard, (DES). While the Rivest patent discloses the RSA algorithm, which is widely used in electronic commerce protocols. The RSA uses a public and private key. DES, also known as secret-key cryptography or symmetric cryptography is based on a 56-bit key to encrypt. This form of cryptography uses identical secret keys. They are unique in the ideal world and unknowable to anyone outside the sender or receiver. The secret key is used to encode plain text into ciphertext. The sender can send the ciphertext to the receiver via any public or insecure communication medium. After receiving the ciphertext, the receiver decrypts it with the secret key in order to find the plain text.

U.S. Pat. 102/030 reveals a method to secure the Internet. No. 6,070,154 to Tavor et al. entitled:?Internet Credit Card Security It is incorporated herein in its entirety and used for all purposes. This patent describes a method of transmitting credit card numbers securely via the Internet. The security is achieved by sending the credit card number in multiple transmissions, each one containing part. U.S. Patent. Another method is disclosed. No. No. It is included in its entirety as if fully described herein. This suggests the use of two or more non-secured network to protect transaction security. U.S. Pat. No. 7,774,592 to Ishikawa et al. entitled “Encryption Communication method”, which is included in its entirety as if fully described herein, discloses an encryption-based communication system that executes, on an unspecified network to which many nodes are connected to, secure communication between nodes of a particular group.

The Internet is becoming more popular for multimedia transmissions, including audio and video. There are many audio services available, including Internet-radio stations (IPTV) and VoIP (Voice over IP). Video conferencing and IPTV (IP Television) are two examples of video services that can be delivered over the Internet. The multimedia service is usually real-time or near-real-time and therefore sensitive to Internet delays. Two-way services, such as VoIP, telephony services or video-conferencing, are particularly sensitive to delays. Some cases render encryption impossible due to the delay caused by encryption and the associated hardware/software cost. Therefore, it is not easy to secure enough capacity of the Internet accessible by users to endure real-time communication applications such as Internet games, chatting, VoIP, MoIP (Multimedia-over-IP), etc. This could lead to data loss, delays, or severe jitter during communication. The following chapters from the publication 1-587005-001-3 published by Cisco Systems Inc. (July 1999) and titled: ‘Internetworking Technologies Handbook?, are about multimedia over the Internet. They are all incorporated herein in their entirety for any purpose as if fully described: Chapter 18: Multiservice Access Technologies? (pages 18-1 through 18-10) and Chapter 19: Voice/Data Integration Technologies. ”

The three main types of VoIP systems currently in widespread use are: those that use the ITU-T H.323 protocol and those that use the SIP protocol. The International Telecommunications Union (ITU) developed H.323, a standard for teleconferencing. It allows full multimedia audio, video, and data transmission between two or more participants and is optimized to support large networks. H.323 can be used over networks using other transport protocols than TCP/IP. Although H.323 remains a vital protocol, it has been discontinued from consumer VoIP products. This is due to its inability to work with firewalls that protect multiple applications. This system is best suited for large organizations with the technical skills necessary to overcome these issues.

“SIP” (for Session Initiation Protocol), is an Internet Engineering Task Force standard signaling protocol that allows for teleconferencing and telephony. It also supports instant messaging, notification, event notification, and presence. It is used to establish and manage connections but it does not transport audio or video data. It is the most commonly used protocol to manage Internet telephony. SIP, like the IETF protocols is described in a variety of RFCs, primarily RFC 3261. SIP-based VoIP implementations can send encoded voice data over the internet in many ways. RFC 3550 defines the Real-time Transport Protocol (RTP) as the most common implementation. RTP and SIP are both implemented on UDP. This connectionless protocol can cause problems with some types of firewalls and routers. Useable SIP phones must also use STUN (for Simple Transversal of UDP Over NAT), a protocol described in RFC 3489. This protocol allows a client behind a NAT router, to determine its external IP address and type of NAT device.

“Onion routing (OR), is a method for anonymous communication over the Internet and any other computer network. Multiple messages are encrypted, and sent to multiple network nodes known as onion routers. Each onion router removes an encryption layer to reveal routing instructions and then sends the message on to the next router. These intermediary nodes are not able to see the contents or origin of the message. The messages between routers are encrypted to prevent an adversary listening in on the content of the message. It is possible to communicate anonymously with other routers using onion routing and mix cascades. However, it is not necessary that each router be trusted. Each router in an OR network receives messages and re-encrypts them before transmitting them to another onion router. Onion routing (OR) protects the sender and recipient’s privacy while protecting the message content as it travels through a network. This is done according to the principle known as Chaum mix cascades. Messages travel from source to destination using a series of proxy (?onion routes?). These re-route messages in an unpredictable path.

Routing onions are data structures that allow for multiple messages to be transmitted over a number of paths. The router that creates an onion selects one of the many onion routers randomly and generates a message. It then provides the router with symmetric keys to decrypt messages and tells it which router is next. These messages and messages for subsequent routers are encrypted using the public key of the router. This creates a multilayered structure in which it is necessary for one to decrypt each layer of the onion to reach the inner layer. U.S. Patent. No. Reed et.al. 6,266,704 entitled:?Onion Routing Network to Securely Move Data through Communication Networks?. This document is included in its entirety and used for all purposes. The publications “Probabilistic Analysis Of Onion Routing In A Black-box Model [Extended abstract]” are other prior art publications that relate to onion routing. WPES’07: Proceedings of ACM Workshop Privacy in Electronic Society 2007,?A Model of Onion Route with Provable Anonymousity? Proceedings of Financial Cryptography and Data Security 2007 and?A model of Onion routing with proven anonymity? were presented in the Financial Cryptography and Data Security 11th International Conference. They were presented by Feigenbaum J. and Johnson J. and Syverson P. in the Proceedings of the 2007 Privacy Enhancing Technology Symposium, Springer-Verlag LNCS 4776. By Chaum D. in Communications of the ACM 24-(2), February 1981 and?Valet Services : Improving HiddenServers with a Personal Touch? Proceedings of the 2006 Privacy Enhancing Technology Workshop, Springer-Verlag LNCS 4285. Both by Overlier L., Syverson, P., publications ‘Making Anonymous Communication? Generation 2 Onion Routing briefing slides. Center for High Assurance Computer Systems. Naval Research Laboratory. Presented at the National Science Foundation. June. 8th, 2004 by Syverson, publications ‘Onion routing access configurations,?DISCEX2000: Proceedings of DARPA Information Survival Conference and Exposition? Volume I Hilton Head. S.C. IEEE CS Press. January 2000.?Onion routing for anonymous and private internet connections,? Communications of the ACM. 42, num. 2, February 1999. IEEE Journal on Selected Areas in Communication Special Issue on Copyright and Protection, 1998. All by Syverson, Reed M. G. and Goldschlag M., publication ‘Towards an Analysis of ONION Routing Security and ‘Workshop on Design Issues in Unobservability and Anonymity Berkeley, Calif. July 2000.

“?Tor? “?Tor? is an anonymizing network that uses the principles of ‘onion routing?. It involves a system that selects a random route for each connection via the Tor network routers. This is the?exit server?. After leaving the Tor cloud, the server sends the data to its final recipient. It is impossible to observe the?exit node continuously at this point. It is impossible to identify the sender of the message. The?Tor project has the following information: project in http://www.torproject.org. U.S. Patent Application Publication 2010, p. Rieger et. al. describes the Tor network concept in Proceedings of the 13th USENIX Security Symposium August 2004 by Dingledine R. and Mathewson N., Syverson PP. in publication ‘Tor Protocol specification? Dingledine R., Mathewson N., in publication “Tor Directory Protocol Version 3?” and publication “TC: A Tor Control Protocol?” Downloaded from the Tor website, these are incorporated in full for all purposes as if set forth fully herein.

A bus is a subsystem of computer architecture that consists of a conductor or group of conductors. It is used to carry signals, data, power and serves as a common connection among circuits, devices, or other components. A bus is used to transfer data between computer components, computers, or between peripheral devices. A bus can be implemented in many ways. It may be parallel (where each data word is carried in parallel along multiple electrical conductors), serial (such a bit-serial connection), or a combination thereof. The bus can also be wired in different topologies, such as multi-drop (electrical paralel) or daisy chain. A bus can also be used to implement a communication network that uses hubs and switches. Buses can be either internal, which is often implemented as a passive backplane or motherboard conductors. Or external, which is more commonly a cable and may employ passive or active circuitry. A bus can also carry a power signal, which is commonly low-voltage DC power signals, such as 3.3 Volts DC, 5 VDC, 12VDC and 48VDC. The bus width is the sum of the lines and wires in a parallel bus.

FIG. shows a non-limiting example of a 160-processing computer system that uses a memory-mapped I/O scheme (Input/Output). 16. The bus 164 connects a processor 163, which may be used as a CPU?Central Processing Unit, to a memory 162 or I/O circuitry (161). The bus 164 consists of three buses: an address bus 166, a data bus 167, and a control bus 165. The address bus 163 carries the address of the processor 163, which is related to the physical or imaginary location in memory 162, or physical/virtual specific I/O components. The data bus 167 contains the value that will be read or written. The control bus 163 carries control information between processor 163 (or other devices), such as signals or commands from processor 163 that report to processor 163 the status and various devices like memory 162 and I/O 16.1. It is also used for controlling and supporting data bus 167 and address bus 166. One line on the control bus can be used to indicate whether CPU 163 is reading from or writing to the memory 162 (R/W). Either the address bus 166 or the data bus167 can be carried on separate conductors (nonmultiplexed buses) or they may be carried together using time-multiplexing.

FIG. 170 shows a sub-system 170 that illustrates a schematic, non-limiting example of the detailed coupling of a memory components 171 to address bus 166, data bus 167, and control bus 160. 17. The memory 171 can store 256 bytes (256*8). It is addressable via 8 address lines A7, A6 and A5 (MSB?) Most Significant Bit), A6 and A5 line 176 b and A5 line 176 c. A4 line 176 d, and A4 line 176 e. A3 line 176 f. A4 line 176 d. A3 line 176 e. A4 line 176 c. A3 line 176 176 g, A1line 176 176 g, and A0 line 176 h. The processor can specify an address using the address bus 166, and the addressbus 176 may be connected to receive the address via the address logic circuit 174. The address circuit 174 can be either a buffer or line-driver or a latch or register which are often used in multiplexed bus environments. Data values that are to be written or read from memory 171 can be coupled to and from data logic 175. This may be a simple buffer or line-driver or a bidirectional latch or register, which are common in multiplexed bus environments. D7 (MSB), D6, D5 (177 b), D5 line 177 c; D4 line 177 d; D3 line 177 e; D3 line 177 d; D4 line 177 e; D3 line 177 f; D2 line 177 f and D1 line 177 g respectively. These are connected by D7 line 177 a to D7 line 177 b and D6 line 177 b. The control block 172 connects with the control bus 165. It may also be connected to the address bus 166 or the data bus 176, and produces the signal R/W 173. This connects to memory 171 and indicates a Write cycle (R/W=Logic?0?). or a Read cycle. An example processor that may not be limited to 80186 and 80188 can be found at Intel Corporation, Santa-Clara (Calif.), USA. The manual?80186/80188 16-Bit High-Integration Microprocessors? describes the 80186 and details about its memory connections. Intel Corporation. It is incorporated herein in its entirety and used for all purposes. Motorola Inc., located at. Schaumburg, Ill., USA. The manual MC68360 Quad Integrated Communications Control Controller?User Manual?describes the MC68360 along with its memory connections. Motorola, Inc., is incorporated herein in its entirety. Although the 8-bit address bus was shown above, many other widths of address bus are used in common, including 32-bit, 64-bit, and 16-bit. Similar to the above example of an 8-bit wide data bus, other widths are also common such as 16-bit 32-bit or 64-bit width.

“It is necessary to protect data stored in a memory against authorized use. The terms “memory” and “storage” are interchangeable. The terms?memory? and?storage are interchangeable herein. Both?storage’ and?retention? are interchangeable herein. They refer to any physical component that can store or retain information (that can later be retrieved), such as digital data, usually for use in a computer or another digital electronic device. Memory can be used to store computer programs, data, and any other sequence of instructions. It also stores files, text, numbers, audio, and video. Information can be stored in a variety of physical media, including electrostatic, magnetic, optical, chemical and electrical. A memory can be stored in an Integrated Circuit (IC), also known as. Chip or microchip. The memory can also be packaged functionally assembled of electronic components (module) as an alternative or additional form. This module could be based on a PCB, or a single in-line memory module (or DIMM), which is standardized according to the JEDEC JESD-21C standard. A memory can also be in the form a separate rigidly enclosed box, such as a hard-disk drive.

“Semiconductor memory may be based on Silicon-On-Insulator (SOI) technology, where a layered silicon-insulator-silicon substrate is used in place of conventional silicon substrates in semiconductor manufacturing, especially microelectronics, to reduce parasitic device capacitance and thereby improving performance. SOI-based devices are different from traditional silicon-built devices because the silicon junction is higher than an electrical insulator (typically silicon dioxide or sapphire). These types of devices, also known as silicon on sapphire or SOS are less common. SOI-based memories include Zero-capacitor RAM and Twin Transistor RAM.

A memory can be volatile if it requires continuous power to keep the stored information, such as RAM (Random Access Memory) or DRAM (DynamicRAM) or SRAM(StaticRAM). Or, it could be non-volatile, which doesn’t require a power supply. Examples of non-volatile memories include Flash memory, EPROM and EEPROM. Volatile memories can be used for long-term storage, while non-volatile memory is more appropriate where quick access to memory is needed. Volatile memory can be dynamic where stored information must be refreshed periodically (such as DRAM re-reads and then rewritten), or static where power is not required. A small battery can be connected to a volatile memory that consumes low power, which allows it to be used as a non-volatile storage device.

A memory can be read/write memory (or mutable storage). This means that data may be overwritten multiple times and often at any time. A memory could also be read/write (or mutable storage) where data can be overwritten more than once and typically stored at any time, such as RAM or Hard Disk Drive (HDD). The information is irrevocable once it has been written. It cannot be modified and can only be read. This is sometimes called Write Once Read Many (WORM). Data may be written during the manufacturing of the memory. This includes mask-programmable ROM, which is where data is written to the memory as a part or the IC fabrication. Alternately, data can be written once to the “write once” storage. at some point after manufacture, such a Programmable Read-Only Memory or Compact Disc-Recordable (CDR).

“Random access” is a way to access a memory. Random access is a method where all storage locations can be accessed at the same time. This includes RAM, ROM, and most semiconductor-based memories. A memory could also be of sequential access. A memory may also be of?sequential access? type. This means that the pieces of information are stored or gathered in a sequential order. The time it takes to access a piece of information or an address will depend on when the last piece was accessed. Common memory devices are location-addressable, where each individually accessible unit of data in storage is selected using its numerical memory address. A memory can also be file-addressable. This means that the information is broken into files of variable length and selected using a directory (usually a human-readable name) or content-addressable. Each unit of information in storage is selected on the basis (or part) of the stored content. Additional software, hardware, or both are often required for file addressability or content addressability.

“There are many storage technologies that can be used to store the data. Commonly, semiconductor, magnetic and optical media are used. Semiconductor-based mediums are based on transistors and capacitors as well as other electronic components within an IC. These include RAM, ROM, Solid-State Drives(SSDs) and Solid-State Drives. Flash memory is an important non-volatile semiconductor technology. It can be electrically erased or reprogrammed. Flash memory can be based on NOR, NAND or NAND based single level cells (SLC), or multi-level cell (MLC), which are made from floating-gate semiconductors. Personal and laptop computers, PDAs (digital audio players (MP3 players), mobile phones, PDAs, digital cameras, smartphones, synthesizers and video games consoles are just a few examples of flash memory applications. Magnetic storage stores the information using different types of magnetization on a magnetically coated or ferromagnetic surface. Access to the information can be made by transducers or read/write heads. Floppy-disks, magnetic tape data storage, and HDD are all examples of magnetic-based memories. An optical disk is commonly used in optical storage. This optical disc stores information on the surface of a circular disk. The information can be read by shining a laser diode onto the disc and watching the reflection. Permanent (read-only media), once-only (write once media), or reversible. Examples of read-only storage that are commonly used to distribute digital information, such as music, audio and video, include DVD-ROM, CD-ROM, BDROM (BD?Bluray Disc), and DVD-ROM. CD-R (DVD-R), DVD+R, BD-R and BD?R are all examples of write-once storage. Non-limiting examples include CD-RW (Compact Disc ReWritable), DVDRW, DVD+RW and DVD-RAM. BD-RE is Blu-ray Disc Recordable Erasable. Magneto-optical disk storage is another non-limiting example. This is where information can be read optically and stored in the magnetic state on a ferrromagnetic surface. 3D optical storage is an optical storage that allows information to be stored and/or retrieved with three-dimensional resolution.

A removable storage medium can be designed to be removed from the computer and installed or inserted in it by a person. This is usually done without any tools and without powering down the computer or associated drive. This capability is useful for data storage, transporting between computers, as well as for purchasing and selling software. A reader, player, writer or burner can read the medium. Or, a writer or reader may use the medium to write and read the data. The form factor of an optical or magnetic-based medium is commonly a disk. This is a round plate that contains the data. A disk drive is the machine that reads and writes data to a disk. Internal disk drives can be integrated into the computer enclosure or externally housed in a separate box connected to the computer. Floppy disks can be read or written to by a floppy disk. CD-RW (Compact Disc ReWritable) is an example of a removable optical disc. Commonly, a non-volatile, removable semiconductor-based storage medium is used and is called a memory card. A memory card, a small storage device that is often based on flash memory and can be read using a card reader.

A memory can be accessed by a parallel connection (in which each data word is carried in parallel along multiple electrical conductors or wiring), or via serial bus (such bit-serial connections), such as USB, Ethernet based upon IEEE802.3 standard or a combination thereof. You can wire the connection in various topologies, such as point-to-point or multi-drop (electrical paralel), or daisy chain. The memory can be powered by a designated port or connector or via a power signal carried on the bus such as SATA and USB.

“A memory can be provided in accordance with a standard. This defines its form factor (physical size and shape, as well as electrical connections (power and data interface). An appropriate slot, also known as a. An expansion slot) is a place where a standard-based memory can be inserted to or removed from a suitable slot (a.k.a.. One non-limiting example is a memory card that uses a PC Card form factor (or JEIDA4.1) and can be mounted into a compatible PCMCIA slot. It supports 16- or 32-bit width interfaces, and can be connected via 68 pins connectors. CardBus may also be used according to PCMCIA5.0. One example is the SD (Secure Digital Card) memory, which conforms to the standard set by the SD Card Association (SDA). This card is used in many small devices, such as mobile phones, digital cameras, audio players, and digital video camcorders. You can also use other types of memory cards, including CompactFlash (CF), MiniSD Card, MicroSD Card and xD?Picture Card.

“Another non-limiting example is the provision of a memory as a USB flash drive, which is a portable enclosed card that plugs into an USB port on a computer and communicates with a USB host. These flash-based memory drives are also known as?thumb drives’,?jump drivers?. These flash-based memory drives are also known as?thumb drives?,?jump drives?, and?memory sticks’. Such USB mass storage devices and others are described in ?Chapter 1: Mass Storage basics?, downloaded October 2011 from: http://www.lvr.com/files/usb_mass_storage_chapter_1.pdf, which is incorporated in its entirety for all purposes as if fully set forth herein. Another example is that the memory can be fitted into a drive bay within a computer enclosure. These drive bays are typically standard-sized and can be used to store disk drives. Drives can be secured using screws or a tool-less fastener. The current standard is the 3.5 inch (3.5?). bays are described in the SFF standard specifications SFF-8300 & SFF-8301. These specifications were also incorporated into EIA standard EIA-477.

Computer-related storage used to be divided into main memory, secondary, and tertiary storages. They had different latency (access times), capacities, and sizes. The memory that could be accessed directly by the CPU was called the main memory. It typically contained the program to execute by the processor. Secondary storage, also known as external memory or auxiliary storage, was a memory that is not directly accessible by the CPU. It typically has a larger storage capacity and requires input/output channels. Tertiary storage was mass storage media that is often associated with dismountable media. This media was used to archive rarely-accessed information. Accessing a specific location takes a few seconds for primary storage, a few milliseconds for secondary storage and a few seconds for tertiary. A memory’s capacity is often displayed in bytes (B), with the prefix?K? The prefix?M is used to indicate kilo=210=10241=1024, and the prefix?K? is used to denote mega=220=10242=1,048,576, the prefix ?G? is used to denote giga=230=10243=1,073,741,824, and the prefix ?T? is used to denote tera=240=10244=1,099,511,627,776.”

Direct-attached Storage (DAS) is a type of memory that connects directly to a host, computer server, workstation or server. Often, there is no network between the two. A number of hard drives (HDDs) can be connected to a computer or processor via a Host Bus adapter (HBA). SATA, eSATA and SCSI are all common connections. A memory can also be part of a Network Attached Storage (NAS) where a self-contained file-level storage (typically arranged like a server), is connected to a router, hub, switch, or router, allowing data sharing with other devices (such a heterogeneous client). NAS can be configured using either software or hardware. This allows for faster data access, simpler administration and easier configuration. NAS is often associated with a LAN and provides an Ethernet interface based upon IEEE802.3. This standard can be used for 10/100BaseT/TX, 10 GbE/10 Gigabit Ethernet (10 GE, 10 GbE, or 10 Gigabit Ethernet per IEEE Std 802.3ae 2002as standard), 40 Gigabit Ethernet (20 GbE) or 100 Gigabit Ethernet (1100 GbE per Ethernet standard IEEE P802.3ba). Another alternative is to use a Memory Area Network (SAN) as a storage device. This is a network or sub-network that shares storage devices such as tape libraries, disk arrays, and optical jukeboxes. It’s a high-speed, commonly-dedicated network. The SAN allows multiple servers or computers to access multiple storage devices via a network like WAN or LAN. SAN uses a Fibre Channel fabric topology. This is often made up of a variety of Fibre Channel switches.

“Molecular memory uses molecular species to store data. The molecular component is often referred to as a molecular switching mechanism. It can perform this function using any number of mechanisms including photochromism or charge storage. Each molecule in a molecular memory system contains one bit of data. This allows for massive data storage.

Blu-ray Disc is an optical disc storage medium that is designed to replace DVDs. A blue laser is used to read the disc. This allows information to be stored at a higher density than with DVDs’ longer-wavelength red laser. The disc’s diameter is 120mm, and the disc thickness is 1.2mm of optical plastic disc. This disc is the same size as CDs and DVDs. Blu-ray Discs have 25GB (23.31 GiB per layer), with dual layer discs of 50GB being the norm for feature-length video disks. For BD-XL Bluray rewriter drives, triple layer discs (100 GB), and quadruple layers (118 GB) can be purchased. Blu-ray technology is described in the Whitepaper?Bluray Disc Format. Blu-ray Disc Founders, August 2004. In the brochure ‘Bluray Technology?DISCover infinite storage media?, DISC Archiving Systems B.V. 2010, and in Whitepaper ‘Sustainable Archival Storage?” Optical Archiving: What Are the Benefits? ?, by DISC Archiving Systems B.V.. Downloaded from www.discgroup.com. All are incorporated in their entirety as if they were fully described herein.

Hard Disk Drives (HDDs) are today used for secondary storage in general-purpose computers such as laptops and desktop computers. An HDD is non-volatile digital data storage device that allows for random access. It has rotating platters mounted on a motor-driven spindle inside a protective enclosure. The enclosure can be either internal or external to the computer system enclosure. Magnetically reading from and writing to the platter is done using read/write heads floating on film or air. High-speed interfaces of the serial type are used to interface HDDs. The?Hard-Disk Basics’ article describes common HDDs, including their structure, characteristics, operation, and form factors. This information was compiled by Mehedi Hazan from PCGUIDE.COM and is included in its entirety for all purposes. The controller is an electronic component that connects NAND memory components to the host system. Most SSDs have one. The controller, an embedded processor, executes firmware-level codes and is one of the key factors in SSD performance. The controller performs several functions, including Error correction (ECC), Wear mapping, Bad block mapping and Read scrubbing, read disturb management, Read and Write caching, Garbage collection, and Read scrubbing. Information on SSD technology, marketing, and applications is provided in Martin B. and Dell?DELL SSD Drive (SSD?) Drive?Storage Solutions For Select Poweredge Server? May 2009 and in Janukowicz D. and Reisel D. White-Paper??MLC Solid State Drives : Accelerating SSD Adoption?, IDC #213730 September 2008 and in Dufrasne B. and Blum K., Dubberke U. and IBM Corp. Redbooks?DS8000: Introducing solid state drives?, 2009 which are all incorporated herein for their entirety as if they were fully described in this document.

A bus is a means of connecting peripherals and memories to the processor. Bus can also refer to a communication link, such as Ethernet or any other LAN or PAN, WAN, or WAN communication links. An internal bus, also known as. A bus can be an internal bus (also known as. A bus can also be called an external bus. It is primarily used to connect the motherboard or processor to peripherals and devices outside of the computer system enclosure. Sometimes buses can be used both as internal and external buses. One type of bus is a parallel type. Each word (address, data, etc.) is carried in parallel across multiple wires or conductors. Or, it may be bit-serial where bits are carried sequentially. Buses can support multiple serial links, or lanes that are bonded or aggregated for faster bit-rate transport. ISA (Industry Standard Architecture); EISA [Extended ISA]; NuBus (IEEE 1196); and PATA?Parallel ATA (?Advanced Technology Attachment?) variants like IDE, EIDE (ATAPI), SBus (IEEE 1496), VESA Local Bus, VLB), PCI, ATAPI, SBus, VESA Local Bus, VESA Local Bus, VESA Local Bus, VESA Local Bus, VESA Local Bus, PC/104 Plus, 104 Express, PC/104 Plus, 104 Express, PC/104Plus, PC/104Plus, PC/104 Express, PC/104Plus, PC/104 Express, PC/104Plus, PC/104Plus, PC/104 Plus, ISA (IEEE 1196). Examples of internal serial buses that are not limited to PCIe (PCI Express), Serial ATA(SATA), SMBus and Serial Peripheral Bus/SPI (SPI) bus are non-limiting. HIPPI (High Performance Parallel Interface), IEEE-1284, (Centronix) are non-limiting examples. ), IEEE-488 (a.k.a. GPIB?General Purpose Interface bus) and PC Card/PCMCIA. Examples of external serial buses that are not limited to USB (Universal Serial Bus), eSATA, and IEEE 1394 (a.k.a. FireWire). Futurebus, InfiniBand and SCSI (Small Computer System Interface) are just a few examples of buses that may be either internal or external. The bus medium can be made of electrical conductors. These include copper wire-based cable, which may be twisted-pairs or fiber-optic cables. A bus topology can be point-to-point or multi-drop (electrical paralel) and may also include hubs and switches. Full-duplex buses provide simultaneous, two-way transmission in both directions. Or, a bus can be half-duplex which allows for transmission in only one direction. The characteristics of buses include their throughput (data bit rate), signaling rates, medium length, connectors, medium types, latency and quality-of-service. They also have devices per channel or connection and supported bus width. Configuring a bus to work in a particular environment can be done automatically (hardware- or software-based), or it may require user or installer actions such as jumpers or software settings. Modern buses can be repaired themselves. A spare network (net) is available in case of a failure. Hot-plugging, also known as hot swapping, is a method of connecting or replacing a bus without causing any disruption to the system. The Universal Serial Bus (USB), which allows users to add and remove peripheral components like a keyboard, mouse, or printer, is a well-known example. The bus can be used to carry power signals in a separate cable (using dedicated connectors) or over the same cable that carries digital data (using one connector). Typically, the low-level DC power levels are carried by dedicated wires in the cable. These can be 3.3 VDC or 5 VDC, 12VDC, or any combination thereof. Buses can support master/slave configuration. One connected node is usually a bus master (e.g. the processor-side or the processor), while other nodes (or nodes) are bus slaves. Unless the master has granted permission, a slave cannot connect to or transmit to the bus. Bus timing, strobing or synchronization information can be carried separately (e.g. A clock signal) may be carried over a dedicated channel such as separate wired in a cable or embedded clocking (a.k.a. Self-clocking, in which the timing information is encoded along with the data signal. This is commonly used in line codes like Manchester code. The transition points are where the clock information. Any bus or connection described herein may be based on proprietary specifications or preferably conform to an industry standard (or any variation thereof), such as PCI Express or SAS, SATA or SCSI, PATA or InfiniBand.

Fibre Channel (or FC) is a gigabit speed network technology that is used primarily for storage networking. It has become the standard type of connection for enterprise storage area networks (SANs). Fibre Channel is standardized by the T11 Technical Committee (INCITS), an American National Standards Institute accredited standards committee. Fibre Channel signaling is compatible with both twisted-pair copper wire and fibre-optic cables. Fibre Channel Protocol (FCP), a transport protocol similar to TCP in IP networks, primarily transports SCSI commands via Fibre Channel networks. Three major Fibre Channel topologies describe how many ports are connected together. These are: Point-to?Point (FC?P2P), where two devices connect directly to one another; Arbitrated loops (FC?AL), where all devices are in a loop (similar to token-ring networking); and Switched fabrics (FC?SW), which allows devices or loops to be connected to Fibre Channel switches. This is similar conceptually to modern Ethernet implementations. Fibre Channel devices can support SFP transceiver. Some Fibre Channel devices use LC fiber connector. However, some 1GFC devices use GBIC transceiver. Fibre Channel solutions guide further describes Fibre Channel. by FCIA?Fibre Channel Industry Association (www.fibrechannel.org, September 2010), ?Technology Brief?Fibre Channel Basics?, by Apple Computer, Inc. (May 2006), and Weimer T. of Unylogix, ?Fibre Channel Fundamentals? (available from the Internet October 2011) which can all be incorporated in their entirety as if fully stated herein.

“InfiniBand” is a switched fabric communication link that’s used in enterprise data centers and high-performance computing. It has high throughput, low latency and quality of service. It is also scalable. InfiniBand provides point-to-point, bidirectional serial links that allow processors to connect with high-speed peripherals like disks. InfiniBand offers multicast capabilities in addition to its point-to-point capabilities. You can use multiple signaling rates, and you can bond links together to increase throughput. The SDR serial connection’s communication rate is 2.5 gigabit per sec (Gbit/s), in each direction for each connection. DDR is 5 Gbit/s, QDR 10 Gbit/s. FDR is 14.0625Gbit/s, and EDR 25.78125Gbit/s per lanes. You can aggregate lane data in 4X, 12X, or 12X units. The 12X QDR link can carry 120 Gbit/s raw data or 96 Gbit/s. Most systems are using a 4X aggregate as of 2009. This means that a system can transmit 10 Gbit/s, 20 Gbit/s, or 40 Gbit/s data. InfiniBand uses a switched fabric topology instead of a hierarchical switch network like traditional Ethernet architectures. The network topologies used are either Fat-Tree (Clos), 3D-Torus, or mesh. InfiniBand technology can be further described in the White Paper “Introduction To InfiniBand?” ?, Mellanox technologies Inc., Document Number 2003WP Rev. 1.90 in the document by GrunP. of InfiniBand Trade Association: ‘Introduction To InfiniBand? For End Users?, 2010 and in the White Paper “An Introduction To InfiniBand?” Bringing I/O up-to-speed? Rev. Rev.

“Serial ATA” (SATA, Serial Advanced Technology Attachment) refers to a computer bus interface that connects host bus adapters with mass storage devices like hard drives and optical drives. The Serial ATA International Organization (a.k.a. SATA-IO (serialata.org) is the source of industry compatibility specifications for Serial ATA. It defines three layers of protocol: transport, link and physical. Serial ATA was created to replace the parallel ATA (PATA), which is often referred to as IDE. It offers several advantages over the older interface, including smaller cables and lower costs (7 conductors instead 40), native hot switching, faster data transfer via higher signaling rates and more efficient transfer through an optional I/O queuing protocol. SATA host-adapters communicate with devices via a high speed serial cable that spans two pairs of conductors. Parallel ATA (PATA), on the other hand, used a 16-bit wide databus with many additional support signals and control signals. They also operated at a lower frequency. SATA employs the same basic ATA command-set and ATAPI command set as legacy ATA devices to ensure backward compatibility. The Intel Advanced Host Controller Interface is an open-source host controller interface that has been used widely and published by Intel. It has now become a standard. It allows advanced features such as hotplugging or native command queuing, which are both available in SATA. SATA controllers will typically work in?IDE emulation if AHCI is disabled by the motherboard or chipset. Mode, which prevents access to features of devices if they are not supported by the ATA/IDE standard. SATA defines a data cables with seven conductors (three ground and four active data lines in two pairs), and eight mm wide wafer connectors at each end. SATA cables can be up to 1 meter (3.33 ft) long and connect one motherboard socket with one hard drive. SATA standards specify a different power connector than the four-pin Molex connector used on pre-SATA devices. It is also wafer-based like the data cable. However, its wider 15-pin form prevents accidental mis-identification or forced insertion. eSATA, the?e? standardization was made in 2004. eSATA (the?e? acronym standing for external) is a version of SATA that was standardized in 2004. Although it does not have the same electrical requirements as SATA and has different connectors and cables, the protocol and logical signals are compatible at the (internal SATA) level. SATA employs a point to-point architecture. The physical connection between a controller, a storage device and a controller is not shared with other controllers or storage devices. SATA defines multipliers which allow a single controller to drive multiple storage device. The multiplier acts as a hub, connecting the controller to each storage device. Further information about the SATA bus, protocols, and applications is found in?Serial ATA technology, Technology Brief, Fourth Edition?, Hewlett-Packard Development Company, L.P., TC1108815, Oct. 2011, in white paper ‘External Serial ATA?, Silicon Image, Inc., September 2004 in Krotov I. redpaper:?IBM System x Server Disk Drive Interface Technology, IBM Corp. Document REDP-4791-01, Oct. 10, 2011,?Serial ATA Advanced Host Controller Interface? (AHCI?, Revision 1.0), downloaded from Intel website on October 2011. Also, whitepaper?Serial ATA Technology?, which was downloaded from www.seagate.com in October 2011, are all incorporated herein for all purposes.

“Serial Attached SCSI” (SAS), is a computer bus that uses the standard SCSI command sets and replaces parallel SCSI bus technology. SAS offers backwards-compatibility with second-generation SATA drives. SAS backplanes may be used to connect SATA 3Gbit/s drives, but SAS drives cannot be used to connect to SATA backplanes. The International Committee for Information Technology Standards (INCITS), T10 technical committee, develops and maintains SAS protocols. The SCSI Trade Association promotes this technology. SASA uses full-duplex with Link Aggregation (4-ports wide at 24-Gbit/s) over 10 m external cable and can connect to 255 device ports expanders. The SAS standard defines the voltage levels and connectors at the physical layer. SAS wiring and signaling have largely mirrored the characteristics of SATA, up to 6 Gbit/s. SAS however has more stringent signaling specifications and a larger allowable differential voltage swing to enable longer cabling. SAS-1.0/SAS-11.1 adopted the same physical signaling characteristics as SATA at 1.5 Gbit/s, 3 Gbit/s rates. SAS-2.0 developed a 6 Gbit/s rate which was equivalent to SATA. According to the SCSI Trade Association 12 Gbit/s will be followed by 6 Gbit/s in a future SAS-3.0 specification.

A typical Serial Attached SCiS system includes an initiator, target, a service delivery subsystem, and expanders. An Initiator is a device which initiates task-management and device-service requests to be processed by a target device, and then receives the responses from other target devices. An on-board component of a motherboard, such as many server-oriented motherboards, may serve as an initiator. Or it can be an adapter to an add-on host bus. A Target is a device that contains logical units and target port and which receives task management and device service requests and processes them. It then sends back the same requests to initiator device devices. Target devices could include a hard drive or a disk array. The Service Delivery Subsystem, which is part of an I/O network that transmits information between an initiate and a target, is called an I/O system. A service delivery subsystem is typically made up of cables that connect an initiator to a target, with or without backplanes and expanders. Expanders are devices that facilitate communication between SAS devices and form part of a service-delivery subsystem. Expanders allow multiple SAS End devices and one initiator port to be connected. One or more PHYs can be used to connect an initiator directly to a target. Nearline SAS and NL-SAS drives can be used to connect to traditional enterprise-class SATA drives. They have the SAS interface, head media speed, media speed, and full SAS interface that are typical for classic SAS drives.

“The Serial Attached SCSI Expanders (SAS Expanders), are components that allow communication between large amounts of SAS devices. Expanders can contain one or more expander-ports. Expanders contain at least one SAS Management Protocol target port to manage the device and can also contain SAS devices. An expander could include a Serial-SCSI Protocol target port to allow access to a peripheral device. An expander does not need to be used to interface with a SAS target or initiator, but it allows one initiator to communicate more SAS/SATA targets. Edge expanders are capable of performing both direct and subtractive table routing. An edge expander, also known as an edge extender device set, can connect up to 255 edge expanders. This allows for more SAS devices to be addressed. Each edge expander’s subtractive routing port will be connected to the fanout expander’s PHYs. Further information about the SAS can be found in White Paper?serial attached SCSI and serial compatibility?, Intel Corporation Doc. 0103/OC/EW/PP/1K-254402-001, 2002, in the Product Manual ?Serial Attached SCSI (SAS) Interface Manual?, Publication number: 100293071, Rev. B, Seagate Technology LLC. May 2006. Also in Technology Brief, 4th Edition?Serial Attached SCSI (SAS) Interface Manual?, Publication number: 100293071, Rev.

“USB (Universal Serial Bus), is an industry standard that was developed in the mid-1990s. It defines cables, connectors, and protocols for connecting, communicating, and supplying power to electronic devices and computers. USB was created to standardize the connections of peripherals to computers such as keyboards and pointing devices, digital cameras and portable media players. It also allows for electric power supply and communication. It is now commonplace on smartphones, PDAs, and consoles such as video games consoles, PDAs, and other devices. The USB interface has replaced many older interfaces such as parallel and serial ports as well as separate chargers for mobile devices. The asymmetric USB system is composed of a host, many downstream USB ports, and multiple peripheral device connections in a tiered-star structure. The tiers can be expanded with additional USB hubs. This allows for branching into a tree structure that has up to five levels. Each host controller can have one or more USB ports. A USB host controller could also have multiple host controllers. A single host controller can connect up to 127 devices including hub devices. Hubs are used to link USB devices in series. The root hub is the hub that connects all USB devices. It is usually found in the host controller. One physical USB device can have several sub-devices, which are called device functions. Each function is assigned a single device address by the host.

It is important to protect users’ data from unauthorised access and use. One example is that user data and other confidential information can be stored on hard drives after they are removed from computers or storage systems. This could happen at the end of life. According to NIST 800-88, a federal standard, user data and other confidential information must be erased from storage systems. This is also required by Ponemon Institute document ‘Fourth Annual US Cost of Data Breach Study?, January 2009. Both documents are incorporated herein in their entirety.

These sanitization methods use non-destructive actions such as deleting files or blocking (such as formatting or overwriting externally dedicated software as required by DOD5220). Other techniques, however, use destructive techniques such as disk drive degaussing and physical drive destruction. Disks are removed from disk drives using physical drive destruction. They are then broken up or ground into tiny pieces. Degaussers can be used to erase magnetic data from disk drives. They also create high-intensity magnetic fields that erase all magnetic records on a hard drive or magnetic tape. In-drive encryption with an encryption key is a non-destructive method. Hughes G., Coughlin TC.,?Tutorial Disk Drive Data Sanitization?, describes the different sanitization schemes and requirements for disk drives. (September 2006), Edelstein R. Converge Net Inc.?The Limitation of Software Based Hard Drive Sanitization? The Myth of a Legacy Technology September 2007, in Edelstein R. Converge Net Inc.?Data Loss Prevention – Managing the Final Stage Of the Data Life Cycle Model?A Perspective On Decommissioning Storage Technology? (May 2007), Hughes G. F. and Coughlin T. of Coughling Associates.?Disposal of Disk and Tape Data?, Co-published with the IEEE Computer and Reliability Societies. (IEEE Security & Privacy pg. 29-34, July/August 2009. These are all incorporated as complete documents for all purposes.

“Considering the above, it would be a significant advance in the art to provide an improved storage or networking security method and system that’s simple, secure, cost-effective and faithful, reliable, easy-to use or sanitize, and/or uses existing components, protocols and programs for better security and additional functionality, as well as a better user experience.

“An apparatus and method to improve the security of sending a message that contains a series of messages from sender to recipient over multiple paths on the Internet is described. Interposition relay servers act as link servers between sender and receiver and pass along data. Each of the IP addresses associated with the sender, recipient, and servers is an IP address. The method of sending the message includes the following steps: Associating each message with an intermediate server using an associating scheme; each message slice containing one message element, associating each slice with an intermediate server according a slicing schema, and then sending each message slice along with the IP address to the server that was associated with it. Each message can use a different slicing method and an entirely different associating system. A number of intermediate servers perform the steps of receiving and identifying the message slice, the IP address of recipient, and then sending the message slice to the recipient or another intermediate server. The recipient performs the steps of receiving and identifying multiple message slices and reconstructing at most part of the original message before it was partitioned by the sender.

The sender method steps can be preceded by the step to determine the number of message slice that will be used for message partitioning. Next, the step of splitting the message into the desired number of message segments. It is possible to choose random numbers for the number of message slices that are used in message partitioning. Steps in the sender method may include determining how many message elements are contained in each message slice used for message partitioning. Then, the steps of splitting the message into messages slices with the desired number of message element can be followed. Each message slice may contain the same number of message elements or a distinct number. Each message slice may contain a random number of message elements. A non-overlapping partitioning may be used to include all message elements in one message slice. An overlapping partitioning allows for multiple message elements to be included in different message slices.

The slicing scheme can be based either on sequential partitioning where message elements in one of the message slice follow each other the same way as in the original message or non-sequential division where message elements in one of the slice do not follow one an another as in the original message. Interval sequential partitioning is another option. This means that the message elements in one or several of the message slices can be separated by at most one element in the message.

Each message element may be a bit or nibble, or a byte, or a multibyte word. It may also represent a number, or a character. A sender method could be preceded by padding the message or padding one or several of the message slices following the partition. Partitioning may be based on the current date (or the current TOD) (Time-of-Day).

“The slicing plan or other information about the partitioning can be sent together with one or several of the message slices. Information about a message slice may be sent with another slice. The order in which the message slices are sent may be random or determined by the order of the first message element within each message slice.

The step of encrypting a message before partitioning may precede the method of the sender. Partitioning is performed on encrypted messages, and the steps of decrypting the reconstructed messages follow the steps at the receiver. The method of the sender could be preceded by encryption of at least one message slice after partition at the sender, or at an intermediate host. In this case, the intermediate server may send the message slice before the step of decrypting the message slice. The recipient may also be required to decrypt at least a portion of the message slices before reconstructing the message.

The intermediate servers could be located in different geographical locations such as different cities or states, or even different countries. The intermediate servers can further perform the steps of storing the message slices, the IP addresses of the sender and the recipients.

“The intermediate server method or sender may be preceded by the storage of a list consisting of a succession IP addresses that can be used as source IP addresses by the associating schema. An associating scheme may associate each packet with a message slice with one of the IP addresses on the list. Each message slice is associated to a unique source IP address. Associating schemes may associate a packet containing a message slice with all or part of the source IP addresses. Associating schemes may associate the source IP address with a succession of packets, including the message slices, either sequentially or randomly. The source IP addresses can be randomly selected from the list to be associated with the succession of packets including the message slices.

“The sender and the recipient or an intermediate server can be a separate device or part of a device and may include a memory and a processor that is configured by the memory to perform sender, recipient or intermediate server methods. The sender could be a part of the computer that originates the message. Or, it may be connected to receive the message from another computer via a network, such as an Intranet or LAN, which is commonly used within an enterprise or other business entity. Either the sender or receiver (or intermediate server) can be co-located with a router (e.g. NAT-enabled router), a gateway, or firewall (e.g. sharing an enclosure, an Internet link, a LAN connectivity, an IP address), and connected between a LAN or the Internet.

The intermediate servers can be dedicated servers or integrated with other servers (e.g. sharing an enclosure or an Internet connection, a LAN connector, an IP address or a processor), each having a distinct functionality such as a webserver, online gaming server or instant messaging server. The intermediate server may share an enclosure, an Internet address, an IP adress, a processor or a peripheral device with the other server as part of this integration. The intermediate servers can also share some or all of the communication between the sender and recipient (e.g., transfer of packets containing messages slices), based on either strict routing or LSRR. Or onion routing, such the Tor technique.

“Each of the intermediate servers can execute a method to relay a message from sender to recipient. Each sender and recipient have an IP (Internet Protocol). The intermediate server executes the following steps: receiving from the sender a package that includes the payload message and recipient IP addresses. Next, extracting the message and identifying it, then extracting the IP address of the packet and then sending the message to the recipient, or to an intermediate host. If part of the message has been encrypted, the method may also include the step to decrypt the message once it is received. The method could also include encryption of the message before it is sent.

“In one embodiment, the message is composed a succession message elements. The method executed by any or all of these intermediate servers further involves the steps of splitting the message into a plurality message slices. Each message slice contains one or more message elements and each slice sends the IP address of its sender to the recipient, or to another intermediate server.

The method can be used to deliver audio or video information such as VoIP, video conference, IPTV, or Internet telephony services. The associating or slicing scheme can be random and based upon a random number. This may be based either on a physical process, or an algorithm to generate pseudo-random numbers.

“An intermediate server (or all of them) may continue to execute the steps of dividing the received message slice into a plurality sub-slices. Each sub-slice contains one or more message elements and then sending the subslices with IP addresses to the recipient to another intermediate or recipient server.”

The sender and recipient steps can be executed by either a separate software module or integrated with an application that generated the message or used it to generate the message. A single software module, or the same hardware, may be used as the sender or intermediate server. In this case the sender steps or intermediate server steps are executed by one software module or executed simultaneously by the same processor. A single software module, or the same hardware, may be used as the recipient or intermediate server. In this case, the recipient steps and intermediate server steps are executed by the same software module and executed by the exact same processor.

The sender may determine the slicing and associating schemes. Alternatively, the sender may decide the sender method. In either case, the sending step may include the receiving and storing of the slicing plan. The associating and slicing schemes may be sent via the Internet to the recipient. They can also be sent from one of the intermediate server or another server. The associating and slicing schemes may be periodically received at random, based on a date, or based upon TOD. One method of storing a message is to slicing.

A CAPTCHA can be used to increase communication security. You can add, integrate, embed, or even a portion of the CAPTCHA into a message, or a message slice. One example is that the message, or part thereof, may be embedded within a CAPTCHA. For example, it could use the characters from a message (or message slice) to generate a CAPTCHA image. Another example is that the CAPTCHA contains part or all the information necessary to decrypt the message or slice received. Information about the key public or private used to decrypt the message may be included in a CAPTCHA. One example is that the CAPTCHA might include information about the slicing algorithm or any other information involved in the reconstruction of the message.

“In one aspect, scrambling and descrambling schemes can be used to encrypt and decrypt digital data written onto a memory or storage (or both). The storage (or memory) physical means can be electrostatic, magnetic, acoustic or optical. It may be semiconductor (a.k.a. The memory may be semiconductor (a.k.a. The memory can be either volatile or non-volatile and may be static or dynamic. You can write the memory more than once or as part of the manufacturing process, or later (e.g. The memory can be written by the user using a specific equipment or as part a normal operation. Random or sequential access may be used. The memory can be file-addressable, location-addressable, or content-addressable. A non-removable media or a removable medium may be used. Access to a memory can be made via a bus or parallel connection. It may also be powered by a dedicated connection. Memory is often characterized by its access time and capacity. It can also be portable or enclosed in an enclosure. It could be a DAS or a part of NAS, SAN or SAN.

A bus can be used for any connection, including the connection of peripherals and memory to a processor. Buses can also be considered communication links (e.g. Ethernet or any other LAN/PAN/WAN communication links. Buses can be internal buses, external buses or both. Buses can be parallel or bit-serial. Buses can be built on one or multiple serial links, or lanes. A bus medium can be electrically conductor-based, such as wires and cables, or it may be based upon a fiberoptic cable. A bus topology can be point-to-point or multi-drop (electrical paralel) and may also include a daisy-chain. It may also use hubs and switches. Point-to-point buses can be either full-duplex or half-duplex. A bus can also be built using proprietary specifications or may be substantially or fully compliant with an industry standard (or any variation thereof). It may also be hot-pluggable. A bus can be designed to carry digital data signals only, or it may also carry power signals (commonly DC voltages), in separate and dedicated cables or connectors. Or, the bus may carry both power and digital data over one cable. Buses can be configured to support master/slave. Buses may have a separate timing signal, or self-clocking line code.

“In one aspect, a memory scrambler that connects between a processor (directly or via bus) and the address word (directly or via bus) is disclosed. Addressing the memory converts an address word to another according to a conversion scheme. This scheme may include a one-to-1 mapping scheme. A data scrambler can also be connected between a processor (directly or via bus) and the memory (directly or via bus). The data scrambler converts data words to be written to the memory according to a conversion schema, which could be a one to-one mapping scheme. In order to reconstruct the original word, an inverse conversion scheme can be applied to data words read from the memory. Each of the data or address scramblers can be connected-based. This means that the significance of each address or data bit in the address, or data words is altered. Any combination of logic may be used to create the data or address scramblers. This could be using discrete logic gates, ASICs and PLDs as well as memory, processors and any combination thereof. The memory can be either non-removable, or removable. In this case, the written information is scrambled using address or data scrambling. It cannot be read without going through the appropriate de-scrambling process.

“The scrambling scheme, or any of the scramblers, may be programmed once and then reset again. This could happen in manufacturing or by the user who uses a dedicated programer or on-board programming during system operation. Alternatively or in addition, the scrambling scheme may be field changed and overwritten/programmable in the field, such as by the processor accessing the memory. The scramblers can be volatile or nonvolatile. One scrambler (or both) could include a random generator. This generator is used to write random numbers in certain parts of the memory such as during write cycles.

Both address and data scramblers can be used simultaneously to access the same memory. The scrambler can use the same, similar, or different scrambling strategies, handle the same or differing bus widths, or be based on different implementations or component types. Two scramblers can be combined to share an enclosure, mechanical support and connectors. Power sources, interfaces, and power sources may also be shared. If the address word, data word, or both are carried using bit-serial connections or communications such as serial buses, the address or data word is first extracted from the processor. The address or data word is then identified and converted and then inserted into the serial stream connected with the memory. Converting the serial address or data word to parallel, converting it to another parallel address word (or data word) according to a conversion schema, then serializing and combining the parallel converted words over the bit-serial communication.

An adapter can include a data scrambler or address scrambler or both. It also may have encryption and interfaces that allow for connection to the processor (directly, via a bus, or via a bus). Passive or active electronic circuits may be included in the adapter or any portion thereof. The adapter or any part of it may be powered by the power source (AC, DC), or the power supply that powers the processor, or from the power sources (AC, DC), or the power supply that powers the memory, or both. Alternately, the adapter or any part thereof may be powered by a separate power source or supply. Alternately, the adapter or any part thereof may be powered by the bus or another connection to the processor. The connection or bus may also power the memory. Alternately, the adapter can be powered by a separate power source or supply. Alternately, the adapter can be powered by the bus or another connection to the memory. It may also power the processor directly via the connection or bus. A dedicated cable may be used to power the adapter via a connection (such a connector or bus), where it has power-dedicated wires/conductors, or by using power/data carried over the same wires as FDM or the phantom scheme. FDM adapters include circuits that split the power and data signals. These circuits may include a power-pass filter which substantially passes the power signal while substantially stopping it, or a data-passing filter which substantially passes the data signal while substantially stopping its power signal. Alternately, the capacitor may be connected to a transformer centre-tap for seperating power and data signals. Two transformers can be used in phantom schemes. They pass the data signal or signals between the primary windings and the transformers. The power is accessed at their center-taps. An adapter can use a separate power connector to receive power, or a connector that connects to a cable (such a bus cable) carrying both data and power over the same cable.

The adapter (or any portion thereof) can be used to supply power for a device connected to it such as a memory. This powering can be done via a connection or bus that uses a dedicated cable or using the same cable with power-dedicated wires and conductors. Or by using power and data over the same wires like FDM or Phantom scheme. FDM adapters include circuits that combine power and data signals. For example, a power-passing filters substantially pass the power signal while substantially stopping it, or a power-passing and data-passing filter working together substantially passing the data signal while substantially stopping its power signal. A capacitor may also be connected to a transformer centre-tap for power and data signal combining. Two transformers can be used in phantom schemes. They pass the data signal (or signals), between the primary windings and the transformers. The power is supplied at their center-taps.

“Adapters can be manufactured or provided where each one contains a unique address scrambling scheme or distinct data scrambling system, or both.” Alternately, adapters can be manufactured in pairs or with other groups that share the same scrambling scheme.

An adapter, an address/data scrambler or any part thereof can be implemented using software, firmware, hardware or a combination. Hardware can be a separate physical entity. It could take the form of a chip, an IC or a box-shaped enclosure. A PCB may also carry ICs and other electronic parts (such as plug-ins or removable modules). Alternately, or in addition to the above, circuits and functionalities can be integrated with a processor or a memory, or an intermediate device such as a hub, switch or router, or bus expander. If the physical entity is separate, the electrical connections may use standard expansion connectors or bus connectors, as well as edge connectors. Each connection can be keyed, and it is recommended that hot-plugging is supported.

One aspect of the invention is an adapter that connects to a processor and to an address-addressable storage device capable of storing data in an address space. The adapter can be connected to the processor via a bus that is first-type. It may include a first port connecting to a primary bus; a first interface coupled with the first port to receive a first data message associated with an address within the address space; a secondary port connectable with a secondary bus; a third interface coupled with the second port to transmit a second data phrase associated with the address; and a scrambler connecting between the first interface and the second interface for converting the first word to the memory.

“In one embodiment, an adapter is disclosed for connecting to a processor as well as to a memory (such location-addressable memories) with an address space. The bus of the first type connects the memory to a processor. The adapter comprises a first port that connects to a first bus type for connecting the processor to the memory; an interface coupled to this first port to receive a first address from the processor; another interface coupled with the second bus to connect to the memory; a third port that connects to a fourth bus for connecting the memory to the processor; and a third interface coupled to second port to transmit a second address from the address space to memory. A scrambler is connected between the first interface and the second interface to convert the first to a different from the first to a new address word. The scrambler can only be used to convert the first address word to the second. Each of the first and last address words can define a sequence, so the conversion may involve rearranging at least two bits in the address words. Each of the first or second address words can contain multiple bits. A level of significance could be assigned to each bit. The conversion may also include changing the significance of at least two address words.

The scrambler could be based upon logic gates that implement a Boolean function such as PLD memory, discretely packaged logic gates or PLD logic gates. The processor may program the conversion to follow a pre-set scheme. For the processor to address, the scrambler can be connected to the first bus. The second bus type can be the same as the first, or it may be a different type. The memory can be included in the adapter. It may be electrostatic, magnetic, magnetic, acoustic or optical. The memory can be file-addressable and content-addressable. It may also be part of a NAS, SAN, or both. The memory can be once-written and connectable to the processor for reading from or writing to via the second bus. This bus could be either a parallel bus, bit-serial, or both.

“The adapter could include a power supply with a power port that can be powered by a power source. The power supply may have one or more DC outputs to power at least a portion of the memory. An adapter could include a power connector to connect to the power source. The power port can be coupled to this power connector. The second bus could be built on a cable carrying power signals. The adapter may also include a bus connector to connect to the cable.

The memory can be random-accessed or sequentially accessed. It may also be location-based and randomly-accessed. Multiple times can be written to it. The memory can be volatile and may be based on semiconductor storage medium such as RAM, SRAM or DRAM. Non-volatile memory can be based on semiconductor storage medium such as RAM, PROM or EPROM. It may also be Flash-based such as SSD drive, USB?Thumb? drive. Non-volatile magnetic storage media, such as HDD, may be used to store the memory. An optical storage medium, which can be recordable and removable, may be used to store the memory. This may include an optical drive. You can store the media on CD-RW or DVD-RW. An adapter, memory, or both, may be an IC or a PCB with one or more ICs mounted on it, or a box-shaped enclosure.

“The adapter could also include an encryptor/decryptor function that uses an encryption scheme that is coupled to the first and the second interfaces. This allows for the decryption and encryption of digital data between these buses. AES 128, 192, or 256 bits may be used as the encryption scheme.

The first and second buses (or both) can be based on either a PAN or a networked communication link. Either the first or second bus, or both, may be based upon Ethernet. They may also be substantially compliant to IEEE 802.3 standards. Each bus, or both, may be based on either a multi-drop or a daisy chain topology. They may also use half-duplex and full-duplex connections. Each bus may be wired-based, bit-serial, point-to?point and wired-based. A timing, clocking, or strobing signal can be carried over dedicated wires or used in a self-clocking system. The bus medium may be a fiberoptic cable. An adapter may also include a connector to connect to the fiberoptic cable.

Each bus (or both) might use conductors such a bus cable with multiple wires. The adapter may also include a connector to connect to the bus cable. One or more DC, or other power signals may be carried by the bus cable over dedicated wires. Or the same wires that carry the digital data. An adapter could consist of a power/data splitter arrangement with first, second, and third ports. Only the digital data signal is transmitted between the first two ports and only the power signal between the third and fourth ports. The first port is connected to the bus connector. FDM may be used to carry the digital and power signals. The digital data signal is transmitted over a frequency band that is higher than the power signal. A power/data splitter could include an HPF connected between the first two ports and a LPF between the third and fourth ports or a transformer with a capacitor connected between the windings of the transformer. The power and digital signals can be carried in phantom scheme substantially following IEEE 802.3af/2003 or IEEE 802.3at/2009 standards. At least two transformers may be connected to the transformer windings.

The adapter may supply at least a portion of one or more power signals that are DC type and carried over dedicated wires, or carried over the same wires carrying data. An adapter could be a power/data combination arrangement with first, second, and third ports. Only the digital data signal is transmitted between the first two ports and only the power signal between them. The first port is connected to the bus connector. FDM may be used to carry the power and digital signals. The digital data signal is transmitted over a frequency band that is higher than the power signal. A power/data combiner could include an HPF between first and second ports, and a LPF among the first and third port. A transformer and capacitor may be connected to the transformer windings. A phantom scheme may be used to carry power and digital data signals substantially in accordance with IEEE 802.3at/2009 standards. The power/data combiner could include at least two transformers with a center tap connection.

The adapter can be implemented as a separate physical entity such as a die or an IC. A box-shaped enclosure or a PCB carrying ICs or other electronic components. A plug-in card, or a removable enclosure may also be used. The adapter can be integrated with or integrated with the processor.

Each bus may be built on a cable. The connector that connects to the cable may be the first or second port. The cable can be made of conductive wires, or a fiber-optic one. The connector can be used to connect the first and second interfaces. These interfaces allow for both transmitting and receiving data from the cable. The transmitter can use differential signaling, emphasis molding, or self-clocking code. It may also employ error detection and alignment, clock-correction, or channel-bonding. The receiver can use equalization, impedance match termination, or PLL. It may also use decoding and detecting encoded-based errors. The adapter may include a serializer/de-serializer that is coupled between the first interface of the scrambler. This allows for parallel conversion of digital data from the first interface to serialize digital data from the scrambler. The second bus may be a serial bus, and wherein the adapter further comprises a serializer/de-serializer coupled between the second interface and the scrambler, for converting to parallel the digital data received from the second interface and for serializing the digital data received from the scrambler.”

The adapter can be integrated with the memory or the processor, and may include a component that is shared with the memory or processor. The adapter could be a single enclosure that houses the first and third ports, the first interfaces, and the scrambler. It may also include the enclosure housing the processor or memory. An adapter could include a power supply to power at least a portion of it, as well as the power supply being connected to power the processor and memory. The adapter could contain components that are mounted on a substrate, such as a PCB. The substrate can be used to support the processor and memory.

“In one aspect, it is disclosed that a set of two or three adapters is disclosed. Both adapters use scramblers with the same scrambling scheme. The adapters can be mechanically attached, detachable, or both. An adapter can be a plug-in or removable unit that includes the memory and/or the processor. DRM is a method of allowing access to or authentication to scrambled software.

Information is stored in multiple memory locations for one aspect. The information can be split into multiple parts stored in multiple memories. Splitting can be address-based, data-based (such as data word), or both. The required address space is an overlapping or non-overlapping division between the memories. Each address is associated with a memory (or multiple addresses) using a mapping scheme. The mapping can be either sequential or not. Alternately, or in addition to the above mentioned options, the data word may be split using a mapping scheme between the memories. Random data may be used to fill in locations not being used.

The above summary does not cover all aspects of the invention. In fact, the inventor believes that his invention encompasses all possible combinations and derivatives of all aspects listed above. These combinations offer particular benefits that are not specifically mentioned in the summary.

“The principles and operation for an apparatus according the invention can be understood by reference to the drawings and the accompanying description. Similar components appearing in different figures will be denoted with identical reference numerals. These drawings and descriptions are purely conceptual. In practice, one component may implement several functions. Alternately, each function could be implemented by multiple components or devices. The figures and descriptions use identical reference numerals to indicate components that are common to multiple configurations or embodiments. Even if a different suffix is used, identical numerical references refer to functions and actual devices that are identical, substantially the same, or have similar functionality. The components of the invention as described and illustrated in these figures can be assembled and designed in many different ways. The following description of the various embodiments of apparatus, system and method of this invention as illustrated in the figures is not intended as limiting the scope of the invention as claimed. It is only representative of possible embodiments of it.

“In one aspect, a message that will be sent via the Internet is first cut into one or more pieces (?slices?) Each message slice is combined together with the ultimate destination address and slicing data. A modified message that contains the message slice and the ultimate destination address, is sent in one or more packets via the Internet to a relay server. This server is not always associated with the ultimate destination device. The relay server can then identify the ultimate destination, forward the message slice to it (with the source address in the packets), or send it to another relay server which will continue the process.

“In one example, the laptop 12a (?sender?) The laptop 12 a (?sender?) wishes to send a message on the desktop computer 13c (?receiver?) or ?recipient?) via the Internet 11 shown in FIG. 2 above. The credit card number?918283746547 is used to make a commercial commerce transaction. The credit card number must be exchanged between the client who purchased laptop 12a and the customer who purchased store desktop computer 13c. Slice #3 consists of?6547′. The slice #1 is combined with the destination IP address 13 c and the number 1?. The slice #1 is used to identify the slice and is sent as a regular package to the server 14b, which acts as a relay server. As shown in FIG. 30, system 30 shows an example. FIG. 3a shows an example of this. or ?recipient?) The payload of packets is not encrypted with the destination address. The relay server 14b receives packets from source laptop 12a. It decodes destination address from packets payload and adds it to the message. If necessary, it sends the newly formed message over the Internet to destination computer 13c. The packets could use, for example, the 31 c and 31 d routes, 31.e and 31.f paths over the respective communication link 17 f,16 g,16 h, and 17 c. This forms a communication path between the server 14 b and the destination 13 c via routers 15 15 i, 15 d and 15 d as shown in FIG. 3 a.”

Summary for “System and Method for Routing-Based Internet Security”

The Internet is a worldwide network of interconnected computer networks that uses the Internet Protocol Suite (TCP/IP), which includes Transmission Control Protocol (TCP), and the Internet Protocol(IP) to provide services for billions of users around the world. It’s a network of networks made up of thousands of interconnected networks of all types, including public, private, academic, business, government, and other networks. They are connected by many different electronic and optical networking technologies. The Internet provides a wide range of information resources, including interlinked hypertext documents (WWWW) as well as infrastructure for electronic mail. The Internet backbone is the network of data routes that connect large, strategically connected networks to core routers on the Internet. These data routes are hosted at commercial, government, academic, and other high-capacity networks centers. They also host the Internet exchange points, network access points, and network access points that allow Internet traffic to be interchanged between countries, continents, and across oceans. Traffic exchange between Internet service providers (often Tier 1 network) is done through privately negotiated interconnection agreements. This agreement is governed primarily by the principle “settlement-free peering”.

The Internet and its backbone networks do not rely on central control, coordination facilities or global network policies. Its principal architectural features are the ability to place as few network states as possible and control functions in the network elements. Instead, it relies on the endpoints to process most of the processing and ensure data integrity, reliability, and authentication. The high level of redundancy in today’s network links, as well as sophisticated real-time routing protocols, provide alternative routes of communication for load balancing or congestion avoidance.

“The Internet Protocol is responsible to address hosts and route datagrams (packets), from a destination host to a source host across one or more IP network. The Internet Protocol defines two functions for addressing systems. The addresses are used to identify hosts and provide a location service. Each packet is marked with a header that includes the meta-data necessary for delivery. Encapsulation is another name for this process. IP is a connectionless protocol that can be used in a packet switched Link Layer network. It does not require circuit setup before transmission. An upper transport layer protocol addresses the issues of delivery guaranteeing and proper sequencing. It also avoids duplicate delivery and data integrity.

“The Internet protocol design principles assume that the network infrastructure is not inherently reliable at any one network element or transmission medium, and that it is dynamic in terms the availability of links and other nodes. There is no central monitoring or performance measurement facility that monitors or maintains the network’s state. End-to-end principles are used to reduce network complexity. The intelligence of the network is primarily located at the ends of every data transmission. The transmission path routers simply forward packets to next known local gateway matching the routing prefix for destination address.

“The two main components of IP technology are routing and IP addressing. Addressing is how IP hosts are assigned IP addresses. It also describes how sub-networks of IP host address addresses are divided up and grouped together. All hosts perform IP routing, but internetwork routers are the most important. They use either Interior Gateway Protocols or External Gateway Protocols to make IP datagram forwarding decisions across IP-connected networks. Core routers that are part of the Internet backbone use the Border Gateway Protocol, (BGP), as per RFC4098 or Multi-Protocol Label Switching. The following chapters of publication 1-587005-001-3, published by Cisco Systems Inc. in July 1999 and titled “Internetworking Technologies Handbook?”, are included for all purposes. Chapter 5: “Routing basics?” (pages 5-1 through 5-10), Chapter 30,?Internet Protocols? (pages 5-1 to 5-10), Chapter 30:?Internet Protocols? Pages 32-1 to 32-6, Chapter 45: ‘OSI Routing? (pages 45-1 through 45-8) and Chapter 51 :?Security?” (pages 51-1 through 51-12), and IBM Corporation, International Technical Support Organization Redbook documents No. GG24-4756 00 is titled: “Local Area Network Concepts and Products: Management and LAN Operation Systems?, 1st edition May 1996, Redbook document No. GG24-4338 00 is titled: “Introduction To Networking Technologies?”, 1st edition April 1994, Redbook document No. GG24-2580-01 “IP Network Design Guide?”, 2nd Edition June 1999 and Redbook Document No. GG24-3376-01?IP Network Design Guide?, 2nd Edition June 1999 and Redbook Document No.

“A Wireless Mesh Network or WMN (or Wireless Distribution Systems) is a communication system that consists of clients, routers, and gateways connected by radio. These wireless networks can be built on DSR routing protocols. WMNs can be described in a slide show by W. Steven Conner of Intel Corp. titled: ?IEEE 802.11s Tutorial? Presented at the IEEE 802 Plenary in Dallas on November 13, 2006. Slide-show by Eugen Boroci from University Politehnica Bucharest. Titled:?Wireless Mesh Networks Technologies – Architectures, Protocols and Resource Management and Applications?. Also presented in INFOWARE 2009 in Cannes, France. Paper by Joseph D. Camp and Edward W. Knightly, Electrical and Computer Engineering, Rice University in Houston, Texas, USA. All of these papers are incorporated herein for all purposes. This arrangement can also be applied to wireless networks where two clients exchange information via different paths using mesh routers that act as intermediary and relay servers. The routing algorithm in wireless networks is based on MAC addresses. The above discussion on IP addresses is applicable in wireless networks. They use MAC addresses to identify the client initiating the message, as well as mesh routers or gateways serving as relay servers and clients serving as the ultimate destination computers.

FIG. 1a shows a schematic view of an internet-based network 10. 1a . 1a. Various endpoint devices (?hosts?) Different endpoint devices (?hosts?) are shown interconnected via Internet 11. The Internet backbone 11 includes routers 15a-j connected by different bi-directional packet-based communications links 16a-n. The communication links 16a connect routers 15, h, and 15, j. Communication link 16, b connects to routers15 f or 15.j. Communication link 16c connects routings15 h, 15.g, and 16.f. Communication link16 f connects routes15 c and 15.f. Communication link16 g connects Routers15 i and 15.j. Communication link16 k connects to routers15 e. and15 e.a., while communication connection 16 n is used by routers15 a and15 a. Communication link 17a connects laptop12b to the Internet via router15a. Communication link 17b connects router14a to router15 i. Communication link 17c connects router13a to router15 d. Communication link 17d connects router14a to router15 i. Communication link 17e connects router15 i to computer13b. Communication link 17f connects router15 j to computer13 a. Communication link 17g connects router15 g to server14 c, and communication connection 17 i to computer13a to controller15 i to 15 a.

FIG. 1b shows an overview of an IP-based packet 18. 1b . 1b

“The Internet is a packet switching network where packets are sent from their source to their destination through routers. FIG. 20 shows one example of system 20. 2. Laptop 12 a (source?) 2, when laptop 12 a (?source?) wishes to send information desktop computer 13c (?destination?) A packet is created at the source and includes both the destination IP address as well as the source IP address. Different policies and routing algorithms determine how packets are routed over the Internet. The packet is sent first to router 15 j via link 17 g. This schematically can be seen by the dashed line, path 21 a. The packet is sent to router 15, j over link 16, a (designated path 21 b). This forwards it to router 15, h over link 16, a, which then sends it to router 15, g over 16 d (path 21, c). The packet is sent to router 15, g over link 16, e (designated path 21 d). The packet is then forwarded to router 15, f over link 16, k (designated path 21 d). This in turn forwards it to router 15, d over 16 i (path 21, g). The packet is terminated at destination 13 c via the link 17 c. (path 21 h).

“The Internet structure uses a client-server model. The terms “server” and “server computer” are interchangeable. Server? This term refers to a device, computer, or a series thereof that is connected to the Internet. It can be used to provide specific facilities or services for other computers or devices (referred to here as?clients?). Internet. A server is a host with an IP address that executes a “server program” and usually acts as a socket receiver. Many servers offer dedicated functionality, such as web server, Domain Name System server (described RFC 1034/RFC 1035), Dynamic Host Configuration Protocol (DHCP), server (described RFC 2131/RFC 3315), mail server and File Transfer Protocol (FTP), server and database server. The term “client” is also used. The term?client? refers to a program, a device, a computer or series of computers that execute this program. It accesses an Internet server for a service or resource. Commonly, clients initiate connections that may be accepted by a server. Web browsers, for example, are clients that connect with web servers to retrieve web pages. Email clients connect to mail storage server to retrieve mails.

“Network routing is a common term used in the Internet. The network routing devices have the knowledge of the network layout and determine where to forward the packet. In this case, the source only needs to provide the destination IP address. Source routing, a method described by RFC 1940, can be used to determine the path that a packet should follow through the network. Source routing is the method by which a packet travels through the Internet. The sender decides which network route packets should take. Source routing is used. Loose Source Record Route is an alternative form of source routing. The LSRR requires that the sender specifies one or more hops (such an intermediate router) for the packet to pass. Dynamic Source Routing is an efficient and simple on-demand routing protocol that can be used in multi-hop wireless networks of mobile devices such as wireless mesh networks. RFC 4728 describes the DSR. It is intended to reduce the bandwidth used by control packets in ad-hoc wireless networks by eliminating periodic table-update messages, which are required in the table driven approach.

The Internet is a public network that relies on well-known network protocols like TCP/IP. These specifications are widely available and publicly published. A third party (an attacker) can intercept, alter, tamper with or interpret any clear text packets that are being transmitted over the Internet. A third party (?attacker?) may intercept, alter, tamper and interpret any text packets that are sent over the Internet. This makes the Internet unsecure. There are many ways to attack data over the Internet, including network packet sniffers and IP spoofing. It is important to protect sensitive or confidential information that is transmitted over the Internet. This includes bank account details, credit card numbers, criminal records, driver information, vehicle information, loan applications, stock trading, voter information, and any other information. These data are not typically sent as clear text, but encrypted. This means that data is transmitted over the Internet as unreadable data, usually by using a mathematical algorithm.

“Encryption-based mechanisms are typically end-to-end processes that only involve the sender or the receiver. The sender encrypts plain text messages by using an algorithm to transform them. This makes it unreadable to anyone except those with special knowledge. Once the data has been encrypted, it is sent over a network to the receiver. The receiver’s special knowledge allows them to reverse the process and decrypt the message to make it readable. The encryption process commonly involves computing resources such as processing power, storage space and requires time for executing the encryption/decryption algorithm, which may delay the delivery of the message.”

“Transport Layer Security” (TLS) is a non-limiting example of an end-to-end encryption protocol that provides secure communication above the OSI Transport Layer. It uses keyed message authentication codes and symmetric cryptography. TLS clients and servers establish a stateful connection using a handshake process. Various parameters are set during this procedure. This allows for communication that is secure and prevents eavesdropping. RFC 5246 defines TLS 1.2. There are many versions of this protocol in use in web browsing, instant messaging, Internet faxing and voice-over-IP (VoIP) applications. TLS is often used in application design to overlay any of the Transport Layer protocol protocols. This encapsulates the specific protocols of each application, such as HTTP, FTP and SMTP. It has traditionally been used with reliable transport protocols like the Transmission Control Protocol (TCP). It can also be used with datagram-oriented protocols such as the Transmission Control Protocol (TCP) or the Datagram Congestion Control Protocol Protocol (DCCP), which have been standardized using the Datagram Transport Layer Security term (DTLS). TLS is used to secure the World Wide Web traffic that is transmitted via HTTPS. Electronic commerce and asset management are two of the most prominent applications. TLS (RFC 31207) has been increasingly used to protect the Simple Mail Transfer Protocol (SMTP). These applications use public keys certificates to verify endpoint identity. Layer 4 (Transport Layer), and higher layers encryption-based communication protocols are SSH (Secure Shell), and SSL (Secure Socket Layer).

Layer 3 (Network Layer), and lower layer encryption-based protocols include IPsec and L2TP (Layer 2 Tunneling Protocol) both over IPsec and Ethernet over IPsec. IPsec is a protocol suite that encrypts and authenticates each IP packet in a communication session to secure IP communication. RFC 4301 and RFC4309 are the current IPsec standards. It was first described in RFCs 825-1829. Cisco Systems, Inc. has provided an overview of IPsec in the document titled “An Introduction to IP Security(IPSec) encryption?”. This document is incorporated into its entirety for all purposes.

U.S. Pat. explains that there are two common approaches to cryptography. No. No. No. No. The Ehrsam patent describes what is known as Data Encryption Standard, (DES). While the Rivest patent discloses the RSA algorithm, which is widely used in electronic commerce protocols. The RSA uses a public and private key. DES, also known as secret-key cryptography or symmetric cryptography is based on a 56-bit key to encrypt. This form of cryptography uses identical secret keys. They are unique in the ideal world and unknowable to anyone outside the sender or receiver. The secret key is used to encode plain text into ciphertext. The sender can send the ciphertext to the receiver via any public or insecure communication medium. After receiving the ciphertext, the receiver decrypts it with the secret key in order to find the plain text.

U.S. Pat. 102/030 reveals a method to secure the Internet. No. 6,070,154 to Tavor et al. entitled:?Internet Credit Card Security It is incorporated herein in its entirety and used for all purposes. This patent describes a method of transmitting credit card numbers securely via the Internet. The security is achieved by sending the credit card number in multiple transmissions, each one containing part. U.S. Patent. Another method is disclosed. No. No. It is included in its entirety as if fully described herein. This suggests the use of two or more non-secured network to protect transaction security. U.S. Pat. No. 7,774,592 to Ishikawa et al. entitled “Encryption Communication method”, which is included in its entirety as if fully described herein, discloses an encryption-based communication system that executes, on an unspecified network to which many nodes are connected to, secure communication between nodes of a particular group.

The Internet is becoming more popular for multimedia transmissions, including audio and video. There are many audio services available, including Internet-radio stations (IPTV) and VoIP (Voice over IP). Video conferencing and IPTV (IP Television) are two examples of video services that can be delivered over the Internet. The multimedia service is usually real-time or near-real-time and therefore sensitive to Internet delays. Two-way services, such as VoIP, telephony services or video-conferencing, are particularly sensitive to delays. Some cases render encryption impossible due to the delay caused by encryption and the associated hardware/software cost. Therefore, it is not easy to secure enough capacity of the Internet accessible by users to endure real-time communication applications such as Internet games, chatting, VoIP, MoIP (Multimedia-over-IP), etc. This could lead to data loss, delays, or severe jitter during communication. The following chapters from the publication 1-587005-001-3 published by Cisco Systems Inc. (July 1999) and titled: ‘Internetworking Technologies Handbook?, are about multimedia over the Internet. They are all incorporated herein in their entirety for any purpose as if fully described: Chapter 18: Multiservice Access Technologies? (pages 18-1 through 18-10) and Chapter 19: Voice/Data Integration Technologies. ”

The three main types of VoIP systems currently in widespread use are: those that use the ITU-T H.323 protocol and those that use the SIP protocol. The International Telecommunications Union (ITU) developed H.323, a standard for teleconferencing. It allows full multimedia audio, video, and data transmission between two or more participants and is optimized to support large networks. H.323 can be used over networks using other transport protocols than TCP/IP. Although H.323 remains a vital protocol, it has been discontinued from consumer VoIP products. This is due to its inability to work with firewalls that protect multiple applications. This system is best suited for large organizations with the technical skills necessary to overcome these issues.

“SIP” (for Session Initiation Protocol), is an Internet Engineering Task Force standard signaling protocol that allows for teleconferencing and telephony. It also supports instant messaging, notification, event notification, and presence. It is used to establish and manage connections but it does not transport audio or video data. It is the most commonly used protocol to manage Internet telephony. SIP, like the IETF protocols is described in a variety of RFCs, primarily RFC 3261. SIP-based VoIP implementations can send encoded voice data over the internet in many ways. RFC 3550 defines the Real-time Transport Protocol (RTP) as the most common implementation. RTP and SIP are both implemented on UDP. This connectionless protocol can cause problems with some types of firewalls and routers. Useable SIP phones must also use STUN (for Simple Transversal of UDP Over NAT), a protocol described in RFC 3489. This protocol allows a client behind a NAT router, to determine its external IP address and type of NAT device.

“Onion routing (OR), is a method for anonymous communication over the Internet and any other computer network. Multiple messages are encrypted, and sent to multiple network nodes known as onion routers. Each onion router removes an encryption layer to reveal routing instructions and then sends the message on to the next router. These intermediary nodes are not able to see the contents or origin of the message. The messages between routers are encrypted to prevent an adversary listening in on the content of the message. It is possible to communicate anonymously with other routers using onion routing and mix cascades. However, it is not necessary that each router be trusted. Each router in an OR network receives messages and re-encrypts them before transmitting them to another onion router. Onion routing (OR) protects the sender and recipient’s privacy while protecting the message content as it travels through a network. This is done according to the principle known as Chaum mix cascades. Messages travel from source to destination using a series of proxy (?onion routes?). These re-route messages in an unpredictable path.

Routing onions are data structures that allow for multiple messages to be transmitted over a number of paths. The router that creates an onion selects one of the many onion routers randomly and generates a message. It then provides the router with symmetric keys to decrypt messages and tells it which router is next. These messages and messages for subsequent routers are encrypted using the public key of the router. This creates a multilayered structure in which it is necessary for one to decrypt each layer of the onion to reach the inner layer. U.S. Patent. No. Reed et.al. 6,266,704 entitled:?Onion Routing Network to Securely Move Data through Communication Networks?. This document is included in its entirety and used for all purposes. The publications “Probabilistic Analysis Of Onion Routing In A Black-box Model [Extended abstract]” are other prior art publications that relate to onion routing. WPES’07: Proceedings of ACM Workshop Privacy in Electronic Society 2007,?A Model of Onion Route with Provable Anonymousity? Proceedings of Financial Cryptography and Data Security 2007 and?A model of Onion routing with proven anonymity? were presented in the Financial Cryptography and Data Security 11th International Conference. They were presented by Feigenbaum J. and Johnson J. and Syverson P. in the Proceedings of the 2007 Privacy Enhancing Technology Symposium, Springer-Verlag LNCS 4776. By Chaum D. in Communications of the ACM 24-(2), February 1981 and?Valet Services : Improving HiddenServers with a Personal Touch? Proceedings of the 2006 Privacy Enhancing Technology Workshop, Springer-Verlag LNCS 4285. Both by Overlier L., Syverson, P., publications ‘Making Anonymous Communication? Generation 2 Onion Routing briefing slides. Center for High Assurance Computer Systems. Naval Research Laboratory. Presented at the National Science Foundation. June. 8th, 2004 by Syverson, publications ‘Onion routing access configurations,?DISCEX2000: Proceedings of DARPA Information Survival Conference and Exposition? Volume I Hilton Head. S.C. IEEE CS Press. January 2000.?Onion routing for anonymous and private internet connections,? Communications of the ACM. 42, num. 2, February 1999. IEEE Journal on Selected Areas in Communication Special Issue on Copyright and Protection, 1998. All by Syverson, Reed M. G. and Goldschlag M., publication ‘Towards an Analysis of ONION Routing Security and ‘Workshop on Design Issues in Unobservability and Anonymity Berkeley, Calif. July 2000.

“?Tor? “?Tor? is an anonymizing network that uses the principles of ‘onion routing?. It involves a system that selects a random route for each connection via the Tor network routers. This is the?exit server?. After leaving the Tor cloud, the server sends the data to its final recipient. It is impossible to observe the?exit node continuously at this point. It is impossible to identify the sender of the message. The?Tor project has the following information: project in http://www.torproject.org. U.S. Patent Application Publication 2010, p. Rieger et. al. describes the Tor network concept in Proceedings of the 13th USENIX Security Symposium August 2004 by Dingledine R. and Mathewson N., Syverson PP. in publication ‘Tor Protocol specification? Dingledine R., Mathewson N., in publication “Tor Directory Protocol Version 3?” and publication “TC: A Tor Control Protocol?” Downloaded from the Tor website, these are incorporated in full for all purposes as if set forth fully herein.

A bus is a subsystem of computer architecture that consists of a conductor or group of conductors. It is used to carry signals, data, power and serves as a common connection among circuits, devices, or other components. A bus is used to transfer data between computer components, computers, or between peripheral devices. A bus can be implemented in many ways. It may be parallel (where each data word is carried in parallel along multiple electrical conductors), serial (such a bit-serial connection), or a combination thereof. The bus can also be wired in different topologies, such as multi-drop (electrical paralel) or daisy chain. A bus can also be used to implement a communication network that uses hubs and switches. Buses can be either internal, which is often implemented as a passive backplane or motherboard conductors. Or external, which is more commonly a cable and may employ passive or active circuitry. A bus can also carry a power signal, which is commonly low-voltage DC power signals, such as 3.3 Volts DC, 5 VDC, 12VDC and 48VDC. The bus width is the sum of the lines and wires in a parallel bus.

FIG. shows a non-limiting example of a 160-processing computer system that uses a memory-mapped I/O scheme (Input/Output). 16. The bus 164 connects a processor 163, which may be used as a CPU?Central Processing Unit, to a memory 162 or I/O circuitry (161). The bus 164 consists of three buses: an address bus 166, a data bus 167, and a control bus 165. The address bus 163 carries the address of the processor 163, which is related to the physical or imaginary location in memory 162, or physical/virtual specific I/O components. The data bus 167 contains the value that will be read or written. The control bus 163 carries control information between processor 163 (or other devices), such as signals or commands from processor 163 that report to processor 163 the status and various devices like memory 162 and I/O 16.1. It is also used for controlling and supporting data bus 167 and address bus 166. One line on the control bus can be used to indicate whether CPU 163 is reading from or writing to the memory 162 (R/W). Either the address bus 166 or the data bus167 can be carried on separate conductors (nonmultiplexed buses) or they may be carried together using time-multiplexing.

FIG. 170 shows a sub-system 170 that illustrates a schematic, non-limiting example of the detailed coupling of a memory components 171 to address bus 166, data bus 167, and control bus 160. 17. The memory 171 can store 256 bytes (256*8). It is addressable via 8 address lines A7, A6 and A5 (MSB?) Most Significant Bit), A6 and A5 line 176 b and A5 line 176 c. A4 line 176 d, and A4 line 176 e. A3 line 176 f. A4 line 176 d. A3 line 176 e. A4 line 176 c. A3 line 176 176 g, A1line 176 176 g, and A0 line 176 h. The processor can specify an address using the address bus 166, and the addressbus 176 may be connected to receive the address via the address logic circuit 174. The address circuit 174 can be either a buffer or line-driver or a latch or register which are often used in multiplexed bus environments. Data values that are to be written or read from memory 171 can be coupled to and from data logic 175. This may be a simple buffer or line-driver or a bidirectional latch or register, which are common in multiplexed bus environments. D7 (MSB), D6, D5 (177 b), D5 line 177 c; D4 line 177 d; D3 line 177 e; D3 line 177 d; D4 line 177 e; D3 line 177 f; D2 line 177 f and D1 line 177 g respectively. These are connected by D7 line 177 a to D7 line 177 b and D6 line 177 b. The control block 172 connects with the control bus 165. It may also be connected to the address bus 166 or the data bus 176, and produces the signal R/W 173. This connects to memory 171 and indicates a Write cycle (R/W=Logic?0?). or a Read cycle. An example processor that may not be limited to 80186 and 80188 can be found at Intel Corporation, Santa-Clara (Calif.), USA. The manual?80186/80188 16-Bit High-Integration Microprocessors? describes the 80186 and details about its memory connections. Intel Corporation. It is incorporated herein in its entirety and used for all purposes. Motorola Inc., located at. Schaumburg, Ill., USA. The manual MC68360 Quad Integrated Communications Control Controller?User Manual?describes the MC68360 along with its memory connections. Motorola, Inc., is incorporated herein in its entirety. Although the 8-bit address bus was shown above, many other widths of address bus are used in common, including 32-bit, 64-bit, and 16-bit. Similar to the above example of an 8-bit wide data bus, other widths are also common such as 16-bit 32-bit or 64-bit width.

“It is necessary to protect data stored in a memory against authorized use. The terms “memory” and “storage” are interchangeable. The terms?memory? and?storage are interchangeable herein. Both?storage’ and?retention? are interchangeable herein. They refer to any physical component that can store or retain information (that can later be retrieved), such as digital data, usually for use in a computer or another digital electronic device. Memory can be used to store computer programs, data, and any other sequence of instructions. It also stores files, text, numbers, audio, and video. Information can be stored in a variety of physical media, including electrostatic, magnetic, optical, chemical and electrical. A memory can be stored in an Integrated Circuit (IC), also known as. Chip or microchip. The memory can also be packaged functionally assembled of electronic components (module) as an alternative or additional form. This module could be based on a PCB, or a single in-line memory module (or DIMM), which is standardized according to the JEDEC JESD-21C standard. A memory can also be in the form a separate rigidly enclosed box, such as a hard-disk drive.

“Semiconductor memory may be based on Silicon-On-Insulator (SOI) technology, where a layered silicon-insulator-silicon substrate is used in place of conventional silicon substrates in semiconductor manufacturing, especially microelectronics, to reduce parasitic device capacitance and thereby improving performance. SOI-based devices are different from traditional silicon-built devices because the silicon junction is higher than an electrical insulator (typically silicon dioxide or sapphire). These types of devices, also known as silicon on sapphire or SOS are less common. SOI-based memories include Zero-capacitor RAM and Twin Transistor RAM.

A memory can be volatile if it requires continuous power to keep the stored information, such as RAM (Random Access Memory) or DRAM (DynamicRAM) or SRAM(StaticRAM). Or, it could be non-volatile, which doesn’t require a power supply. Examples of non-volatile memories include Flash memory, EPROM and EEPROM. Volatile memories can be used for long-term storage, while non-volatile memory is more appropriate where quick access to memory is needed. Volatile memory can be dynamic where stored information must be refreshed periodically (such as DRAM re-reads and then rewritten), or static where power is not required. A small battery can be connected to a volatile memory that consumes low power, which allows it to be used as a non-volatile storage device.

A memory can be read/write memory (or mutable storage). This means that data may be overwritten multiple times and often at any time. A memory could also be read/write (or mutable storage) where data can be overwritten more than once and typically stored at any time, such as RAM or Hard Disk Drive (HDD). The information is irrevocable once it has been written. It cannot be modified and can only be read. This is sometimes called Write Once Read Many (WORM). Data may be written during the manufacturing of the memory. This includes mask-programmable ROM, which is where data is written to the memory as a part or the IC fabrication. Alternately, data can be written once to the “write once” storage. at some point after manufacture, such a Programmable Read-Only Memory or Compact Disc-Recordable (CDR).

“Random access” is a way to access a memory. Random access is a method where all storage locations can be accessed at the same time. This includes RAM, ROM, and most semiconductor-based memories. A memory could also be of sequential access. A memory may also be of?sequential access? type. This means that the pieces of information are stored or gathered in a sequential order. The time it takes to access a piece of information or an address will depend on when the last piece was accessed. Common memory devices are location-addressable, where each individually accessible unit of data in storage is selected using its numerical memory address. A memory can also be file-addressable. This means that the information is broken into files of variable length and selected using a directory (usually a human-readable name) or content-addressable. Each unit of information in storage is selected on the basis (or part) of the stored content. Additional software, hardware, or both are often required for file addressability or content addressability.

“There are many storage technologies that can be used to store the data. Commonly, semiconductor, magnetic and optical media are used. Semiconductor-based mediums are based on transistors and capacitors as well as other electronic components within an IC. These include RAM, ROM, Solid-State Drives(SSDs) and Solid-State Drives. Flash memory is an important non-volatile semiconductor technology. It can be electrically erased or reprogrammed. Flash memory can be based on NOR, NAND or NAND based single level cells (SLC), or multi-level cell (MLC), which are made from floating-gate semiconductors. Personal and laptop computers, PDAs (digital audio players (MP3 players), mobile phones, PDAs, digital cameras, smartphones, synthesizers and video games consoles are just a few examples of flash memory applications. Magnetic storage stores the information using different types of magnetization on a magnetically coated or ferromagnetic surface. Access to the information can be made by transducers or read/write heads. Floppy-disks, magnetic tape data storage, and HDD are all examples of magnetic-based memories. An optical disk is commonly used in optical storage. This optical disc stores information on the surface of a circular disk. The information can be read by shining a laser diode onto the disc and watching the reflection. Permanent (read-only media), once-only (write once media), or reversible. Examples of read-only storage that are commonly used to distribute digital information, such as music, audio and video, include DVD-ROM, CD-ROM, BDROM (BD?Bluray Disc), and DVD-ROM. CD-R (DVD-R), DVD+R, BD-R and BD?R are all examples of write-once storage. Non-limiting examples include CD-RW (Compact Disc ReWritable), DVDRW, DVD+RW and DVD-RAM. BD-RE is Blu-ray Disc Recordable Erasable. Magneto-optical disk storage is another non-limiting example. This is where information can be read optically and stored in the magnetic state on a ferrromagnetic surface. 3D optical storage is an optical storage that allows information to be stored and/or retrieved with three-dimensional resolution.

A removable storage medium can be designed to be removed from the computer and installed or inserted in it by a person. This is usually done without any tools and without powering down the computer or associated drive. This capability is useful for data storage, transporting between computers, as well as for purchasing and selling software. A reader, player, writer or burner can read the medium. Or, a writer or reader may use the medium to write and read the data. The form factor of an optical or magnetic-based medium is commonly a disk. This is a round plate that contains the data. A disk drive is the machine that reads and writes data to a disk. Internal disk drives can be integrated into the computer enclosure or externally housed in a separate box connected to the computer. Floppy disks can be read or written to by a floppy disk. CD-RW (Compact Disc ReWritable) is an example of a removable optical disc. Commonly, a non-volatile, removable semiconductor-based storage medium is used and is called a memory card. A memory card, a small storage device that is often based on flash memory and can be read using a card reader.

A memory can be accessed by a parallel connection (in which each data word is carried in parallel along multiple electrical conductors or wiring), or via serial bus (such bit-serial connections), such as USB, Ethernet based upon IEEE802.3 standard or a combination thereof. You can wire the connection in various topologies, such as point-to-point or multi-drop (electrical paralel), or daisy chain. The memory can be powered by a designated port or connector or via a power signal carried on the bus such as SATA and USB.

“A memory can be provided in accordance with a standard. This defines its form factor (physical size and shape, as well as electrical connections (power and data interface). An appropriate slot, also known as a. An expansion slot) is a place where a standard-based memory can be inserted to or removed from a suitable slot (a.k.a.. One non-limiting example is a memory card that uses a PC Card form factor (or JEIDA4.1) and can be mounted into a compatible PCMCIA slot. It supports 16- or 32-bit width interfaces, and can be connected via 68 pins connectors. CardBus may also be used according to PCMCIA5.0. One example is the SD (Secure Digital Card) memory, which conforms to the standard set by the SD Card Association (SDA). This card is used in many small devices, such as mobile phones, digital cameras, audio players, and digital video camcorders. You can also use other types of memory cards, including CompactFlash (CF), MiniSD Card, MicroSD Card and xD?Picture Card.

“Another non-limiting example is the provision of a memory as a USB flash drive, which is a portable enclosed card that plugs into an USB port on a computer and communicates with a USB host. These flash-based memory drives are also known as?thumb drives’,?jump drivers?. These flash-based memory drives are also known as?thumb drives?,?jump drives?, and?memory sticks’. Such USB mass storage devices and others are described in ?Chapter 1: Mass Storage basics?, downloaded October 2011 from: http://www.lvr.com/files/usb_mass_storage_chapter_1.pdf, which is incorporated in its entirety for all purposes as if fully set forth herein. Another example is that the memory can be fitted into a drive bay within a computer enclosure. These drive bays are typically standard-sized and can be used to store disk drives. Drives can be secured using screws or a tool-less fastener. The current standard is the 3.5 inch (3.5?). bays are described in the SFF standard specifications SFF-8300 & SFF-8301. These specifications were also incorporated into EIA standard EIA-477.

Computer-related storage used to be divided into main memory, secondary, and tertiary storages. They had different latency (access times), capacities, and sizes. The memory that could be accessed directly by the CPU was called the main memory. It typically contained the program to execute by the processor. Secondary storage, also known as external memory or auxiliary storage, was a memory that is not directly accessible by the CPU. It typically has a larger storage capacity and requires input/output channels. Tertiary storage was mass storage media that is often associated with dismountable media. This media was used to archive rarely-accessed information. Accessing a specific location takes a few seconds for primary storage, a few milliseconds for secondary storage and a few seconds for tertiary. A memory’s capacity is often displayed in bytes (B), with the prefix?K? The prefix?M is used to indicate kilo=210=10241=1024, and the prefix?K? is used to denote mega=220=10242=1,048,576, the prefix ?G? is used to denote giga=230=10243=1,073,741,824, and the prefix ?T? is used to denote tera=240=10244=1,099,511,627,776.”

Direct-attached Storage (DAS) is a type of memory that connects directly to a host, computer server, workstation or server. Often, there is no network between the two. A number of hard drives (HDDs) can be connected to a computer or processor via a Host Bus adapter (HBA). SATA, eSATA and SCSI are all common connections. A memory can also be part of a Network Attached Storage (NAS) where a self-contained file-level storage (typically arranged like a server), is connected to a router, hub, switch, or router, allowing data sharing with other devices (such a heterogeneous client). NAS can be configured using either software or hardware. This allows for faster data access, simpler administration and easier configuration. NAS is often associated with a LAN and provides an Ethernet interface based upon IEEE802.3. This standard can be used for 10/100BaseT/TX, 10 GbE/10 Gigabit Ethernet (10 GE, 10 GbE, or 10 Gigabit Ethernet per IEEE Std 802.3ae 2002as standard), 40 Gigabit Ethernet (20 GbE) or 100 Gigabit Ethernet (1100 GbE per Ethernet standard IEEE P802.3ba). Another alternative is to use a Memory Area Network (SAN) as a storage device. This is a network or sub-network that shares storage devices such as tape libraries, disk arrays, and optical jukeboxes. It’s a high-speed, commonly-dedicated network. The SAN allows multiple servers or computers to access multiple storage devices via a network like WAN or LAN. SAN uses a Fibre Channel fabric topology. This is often made up of a variety of Fibre Channel switches.

“Molecular memory uses molecular species to store data. The molecular component is often referred to as a molecular switching mechanism. It can perform this function using any number of mechanisms including photochromism or charge storage. Each molecule in a molecular memory system contains one bit of data. This allows for massive data storage.

Blu-ray Disc is an optical disc storage medium that is designed to replace DVDs. A blue laser is used to read the disc. This allows information to be stored at a higher density than with DVDs’ longer-wavelength red laser. The disc’s diameter is 120mm, and the disc thickness is 1.2mm of optical plastic disc. This disc is the same size as CDs and DVDs. Blu-ray Discs have 25GB (23.31 GiB per layer), with dual layer discs of 50GB being the norm for feature-length video disks. For BD-XL Bluray rewriter drives, triple layer discs (100 GB), and quadruple layers (118 GB) can be purchased. Blu-ray technology is described in the Whitepaper?Bluray Disc Format. Blu-ray Disc Founders, August 2004. In the brochure ‘Bluray Technology?DISCover infinite storage media?, DISC Archiving Systems B.V. 2010, and in Whitepaper ‘Sustainable Archival Storage?” Optical Archiving: What Are the Benefits? ?, by DISC Archiving Systems B.V.. Downloaded from www.discgroup.com. All are incorporated in their entirety as if they were fully described herein.

Hard Disk Drives (HDDs) are today used for secondary storage in general-purpose computers such as laptops and desktop computers. An HDD is non-volatile digital data storage device that allows for random access. It has rotating platters mounted on a motor-driven spindle inside a protective enclosure. The enclosure can be either internal or external to the computer system enclosure. Magnetically reading from and writing to the platter is done using read/write heads floating on film or air. High-speed interfaces of the serial type are used to interface HDDs. The?Hard-Disk Basics’ article describes common HDDs, including their structure, characteristics, operation, and form factors. This information was compiled by Mehedi Hazan from PCGUIDE.COM and is included in its entirety for all purposes. The controller is an electronic component that connects NAND memory components to the host system. Most SSDs have one. The controller, an embedded processor, executes firmware-level codes and is one of the key factors in SSD performance. The controller performs several functions, including Error correction (ECC), Wear mapping, Bad block mapping and Read scrubbing, read disturb management, Read and Write caching, Garbage collection, and Read scrubbing. Information on SSD technology, marketing, and applications is provided in Martin B. and Dell?DELL SSD Drive (SSD?) Drive?Storage Solutions For Select Poweredge Server? May 2009 and in Janukowicz D. and Reisel D. White-Paper??MLC Solid State Drives : Accelerating SSD Adoption?, IDC #213730 September 2008 and in Dufrasne B. and Blum K., Dubberke U. and IBM Corp. Redbooks?DS8000: Introducing solid state drives?, 2009 which are all incorporated herein for their entirety as if they were fully described in this document.

A bus is a means of connecting peripherals and memories to the processor. Bus can also refer to a communication link, such as Ethernet or any other LAN or PAN, WAN, or WAN communication links. An internal bus, also known as. A bus can be an internal bus (also known as. A bus can also be called an external bus. It is primarily used to connect the motherboard or processor to peripherals and devices outside of the computer system enclosure. Sometimes buses can be used both as internal and external buses. One type of bus is a parallel type. Each word (address, data, etc.) is carried in parallel across multiple wires or conductors. Or, it may be bit-serial where bits are carried sequentially. Buses can support multiple serial links, or lanes that are bonded or aggregated for faster bit-rate transport. ISA (Industry Standard Architecture); EISA [Extended ISA]; NuBus (IEEE 1196); and PATA?Parallel ATA (?Advanced Technology Attachment?) variants like IDE, EIDE (ATAPI), SBus (IEEE 1496), VESA Local Bus, VLB), PCI, ATAPI, SBus, VESA Local Bus, VESA Local Bus, VESA Local Bus, VESA Local Bus, VESA Local Bus, PC/104 Plus, 104 Express, PC/104 Plus, 104 Express, PC/104Plus, PC/104Plus, PC/104 Express, PC/104Plus, PC/104 Express, PC/104Plus, PC/104Plus, PC/104 Plus, ISA (IEEE 1196). Examples of internal serial buses that are not limited to PCIe (PCI Express), Serial ATA(SATA), SMBus and Serial Peripheral Bus/SPI (SPI) bus are non-limiting. HIPPI (High Performance Parallel Interface), IEEE-1284, (Centronix) are non-limiting examples. ), IEEE-488 (a.k.a. GPIB?General Purpose Interface bus) and PC Card/PCMCIA. Examples of external serial buses that are not limited to USB (Universal Serial Bus), eSATA, and IEEE 1394 (a.k.a. FireWire). Futurebus, InfiniBand and SCSI (Small Computer System Interface) are just a few examples of buses that may be either internal or external. The bus medium can be made of electrical conductors. These include copper wire-based cable, which may be twisted-pairs or fiber-optic cables. A bus topology can be point-to-point or multi-drop (electrical paralel) and may also include hubs and switches. Full-duplex buses provide simultaneous, two-way transmission in both directions. Or, a bus can be half-duplex which allows for transmission in only one direction. The characteristics of buses include their throughput (data bit rate), signaling rates, medium length, connectors, medium types, latency and quality-of-service. They also have devices per channel or connection and supported bus width. Configuring a bus to work in a particular environment can be done automatically (hardware- or software-based), or it may require user or installer actions such as jumpers or software settings. Modern buses can be repaired themselves. A spare network (net) is available in case of a failure. Hot-plugging, also known as hot swapping, is a method of connecting or replacing a bus without causing any disruption to the system. The Universal Serial Bus (USB), which allows users to add and remove peripheral components like a keyboard, mouse, or printer, is a well-known example. The bus can be used to carry power signals in a separate cable (using dedicated connectors) or over the same cable that carries digital data (using one connector). Typically, the low-level DC power levels are carried by dedicated wires in the cable. These can be 3.3 VDC or 5 VDC, 12VDC, or any combination thereof. Buses can support master/slave configuration. One connected node is usually a bus master (e.g. the processor-side or the processor), while other nodes (or nodes) are bus slaves. Unless the master has granted permission, a slave cannot connect to or transmit to the bus. Bus timing, strobing or synchronization information can be carried separately (e.g. A clock signal) may be carried over a dedicated channel such as separate wired in a cable or embedded clocking (a.k.a. Self-clocking, in which the timing information is encoded along with the data signal. This is commonly used in line codes like Manchester code. The transition points are where the clock information. Any bus or connection described herein may be based on proprietary specifications or preferably conform to an industry standard (or any variation thereof), such as PCI Express or SAS, SATA or SCSI, PATA or InfiniBand.

Fibre Channel (or FC) is a gigabit speed network technology that is used primarily for storage networking. It has become the standard type of connection for enterprise storage area networks (SANs). Fibre Channel is standardized by the T11 Technical Committee (INCITS), an American National Standards Institute accredited standards committee. Fibre Channel signaling is compatible with both twisted-pair copper wire and fibre-optic cables. Fibre Channel Protocol (FCP), a transport protocol similar to TCP in IP networks, primarily transports SCSI commands via Fibre Channel networks. Three major Fibre Channel topologies describe how many ports are connected together. These are: Point-to?Point (FC?P2P), where two devices connect directly to one another; Arbitrated loops (FC?AL), where all devices are in a loop (similar to token-ring networking); and Switched fabrics (FC?SW), which allows devices or loops to be connected to Fibre Channel switches. This is similar conceptually to modern Ethernet implementations. Fibre Channel devices can support SFP transceiver. Some Fibre Channel devices use LC fiber connector. However, some 1GFC devices use GBIC transceiver. Fibre Channel solutions guide further describes Fibre Channel. by FCIA?Fibre Channel Industry Association (www.fibrechannel.org, September 2010), ?Technology Brief?Fibre Channel Basics?, by Apple Computer, Inc. (May 2006), and Weimer T. of Unylogix, ?Fibre Channel Fundamentals? (available from the Internet October 2011) which can all be incorporated in their entirety as if fully stated herein.

“InfiniBand” is a switched fabric communication link that’s used in enterprise data centers and high-performance computing. It has high throughput, low latency and quality of service. It is also scalable. InfiniBand provides point-to-point, bidirectional serial links that allow processors to connect with high-speed peripherals like disks. InfiniBand offers multicast capabilities in addition to its point-to-point capabilities. You can use multiple signaling rates, and you can bond links together to increase throughput. The SDR serial connection’s communication rate is 2.5 gigabit per sec (Gbit/s), in each direction for each connection. DDR is 5 Gbit/s, QDR 10 Gbit/s. FDR is 14.0625Gbit/s, and EDR 25.78125Gbit/s per lanes. You can aggregate lane data in 4X, 12X, or 12X units. The 12X QDR link can carry 120 Gbit/s raw data or 96 Gbit/s. Most systems are using a 4X aggregate as of 2009. This means that a system can transmit 10 Gbit/s, 20 Gbit/s, or 40 Gbit/s data. InfiniBand uses a switched fabric topology instead of a hierarchical switch network like traditional Ethernet architectures. The network topologies used are either Fat-Tree (Clos), 3D-Torus, or mesh. InfiniBand technology can be further described in the White Paper “Introduction To InfiniBand?” ?, Mellanox technologies Inc., Document Number 2003WP Rev. 1.90 in the document by GrunP. of InfiniBand Trade Association: ‘Introduction To InfiniBand? For End Users?, 2010 and in the White Paper “An Introduction To InfiniBand?” Bringing I/O up-to-speed? Rev. Rev.

“Serial ATA” (SATA, Serial Advanced Technology Attachment) refers to a computer bus interface that connects host bus adapters with mass storage devices like hard drives and optical drives. The Serial ATA International Organization (a.k.a. SATA-IO (serialata.org) is the source of industry compatibility specifications for Serial ATA. It defines three layers of protocol: transport, link and physical. Serial ATA was created to replace the parallel ATA (PATA), which is often referred to as IDE. It offers several advantages over the older interface, including smaller cables and lower costs (7 conductors instead 40), native hot switching, faster data transfer via higher signaling rates and more efficient transfer through an optional I/O queuing protocol. SATA host-adapters communicate with devices via a high speed serial cable that spans two pairs of conductors. Parallel ATA (PATA), on the other hand, used a 16-bit wide databus with many additional support signals and control signals. They also operated at a lower frequency. SATA employs the same basic ATA command-set and ATAPI command set as legacy ATA devices to ensure backward compatibility. The Intel Advanced Host Controller Interface is an open-source host controller interface that has been used widely and published by Intel. It has now become a standard. It allows advanced features such as hotplugging or native command queuing, which are both available in SATA. SATA controllers will typically work in?IDE emulation if AHCI is disabled by the motherboard or chipset. Mode, which prevents access to features of devices if they are not supported by the ATA/IDE standard. SATA defines a data cables with seven conductors (three ground and four active data lines in two pairs), and eight mm wide wafer connectors at each end. SATA cables can be up to 1 meter (3.33 ft) long and connect one motherboard socket with one hard drive. SATA standards specify a different power connector than the four-pin Molex connector used on pre-SATA devices. It is also wafer-based like the data cable. However, its wider 15-pin form prevents accidental mis-identification or forced insertion. eSATA, the?e? standardization was made in 2004. eSATA (the?e? acronym standing for external) is a version of SATA that was standardized in 2004. Although it does not have the same electrical requirements as SATA and has different connectors and cables, the protocol and logical signals are compatible at the (internal SATA) level. SATA employs a point to-point architecture. The physical connection between a controller, a storage device and a controller is not shared with other controllers or storage devices. SATA defines multipliers which allow a single controller to drive multiple storage device. The multiplier acts as a hub, connecting the controller to each storage device. Further information about the SATA bus, protocols, and applications is found in?Serial ATA technology, Technology Brief, Fourth Edition?, Hewlett-Packard Development Company, L.P., TC1108815, Oct. 2011, in white paper ‘External Serial ATA?, Silicon Image, Inc., September 2004 in Krotov I. redpaper:?IBM System x Server Disk Drive Interface Technology, IBM Corp. Document REDP-4791-01, Oct. 10, 2011,?Serial ATA Advanced Host Controller Interface? (AHCI?, Revision 1.0), downloaded from Intel website on October 2011. Also, whitepaper?Serial ATA Technology?, which was downloaded from www.seagate.com in October 2011, are all incorporated herein for all purposes.

“Serial Attached SCSI” (SAS), is a computer bus that uses the standard SCSI command sets and replaces parallel SCSI bus technology. SAS offers backwards-compatibility with second-generation SATA drives. SAS backplanes may be used to connect SATA 3Gbit/s drives, but SAS drives cannot be used to connect to SATA backplanes. The International Committee for Information Technology Standards (INCITS), T10 technical committee, develops and maintains SAS protocols. The SCSI Trade Association promotes this technology. SASA uses full-duplex with Link Aggregation (4-ports wide at 24-Gbit/s) over 10 m external cable and can connect to 255 device ports expanders. The SAS standard defines the voltage levels and connectors at the physical layer. SAS wiring and signaling have largely mirrored the characteristics of SATA, up to 6 Gbit/s. SAS however has more stringent signaling specifications and a larger allowable differential voltage swing to enable longer cabling. SAS-1.0/SAS-11.1 adopted the same physical signaling characteristics as SATA at 1.5 Gbit/s, 3 Gbit/s rates. SAS-2.0 developed a 6 Gbit/s rate which was equivalent to SATA. According to the SCSI Trade Association 12 Gbit/s will be followed by 6 Gbit/s in a future SAS-3.0 specification.

A typical Serial Attached SCiS system includes an initiator, target, a service delivery subsystem, and expanders. An Initiator is a device which initiates task-management and device-service requests to be processed by a target device, and then receives the responses from other target devices. An on-board component of a motherboard, such as many server-oriented motherboards, may serve as an initiator. Or it can be an adapter to an add-on host bus. A Target is a device that contains logical units and target port and which receives task management and device service requests and processes them. It then sends back the same requests to initiator device devices. Target devices could include a hard drive or a disk array. The Service Delivery Subsystem, which is part of an I/O network that transmits information between an initiate and a target, is called an I/O system. A service delivery subsystem is typically made up of cables that connect an initiator to a target, with or without backplanes and expanders. Expanders are devices that facilitate communication between SAS devices and form part of a service-delivery subsystem. Expanders allow multiple SAS End devices and one initiator port to be connected. One or more PHYs can be used to connect an initiator directly to a target. Nearline SAS and NL-SAS drives can be used to connect to traditional enterprise-class SATA drives. They have the SAS interface, head media speed, media speed, and full SAS interface that are typical for classic SAS drives.

“The Serial Attached SCSI Expanders (SAS Expanders), are components that allow communication between large amounts of SAS devices. Expanders can contain one or more expander-ports. Expanders contain at least one SAS Management Protocol target port to manage the device and can also contain SAS devices. An expander could include a Serial-SCSI Protocol target port to allow access to a peripheral device. An expander does not need to be used to interface with a SAS target or initiator, but it allows one initiator to communicate more SAS/SATA targets. Edge expanders are capable of performing both direct and subtractive table routing. An edge expander, also known as an edge extender device set, can connect up to 255 edge expanders. This allows for more SAS devices to be addressed. Each edge expander’s subtractive routing port will be connected to the fanout expander’s PHYs. Further information about the SAS can be found in White Paper?serial attached SCSI and serial compatibility?, Intel Corporation Doc. 0103/OC/EW/PP/1K-254402-001, 2002, in the Product Manual ?Serial Attached SCSI (SAS) Interface Manual?, Publication number: 100293071, Rev. B, Seagate Technology LLC. May 2006. Also in Technology Brief, 4th Edition?Serial Attached SCSI (SAS) Interface Manual?, Publication number: 100293071, Rev.

“USB (Universal Serial Bus), is an industry standard that was developed in the mid-1990s. It defines cables, connectors, and protocols for connecting, communicating, and supplying power to electronic devices and computers. USB was created to standardize the connections of peripherals to computers such as keyboards and pointing devices, digital cameras and portable media players. It also allows for electric power supply and communication. It is now commonplace on smartphones, PDAs, and consoles such as video games consoles, PDAs, and other devices. The USB interface has replaced many older interfaces such as parallel and serial ports as well as separate chargers for mobile devices. The asymmetric USB system is composed of a host, many downstream USB ports, and multiple peripheral device connections in a tiered-star structure. The tiers can be expanded with additional USB hubs. This allows for branching into a tree structure that has up to five levels. Each host controller can have one or more USB ports. A USB host controller could also have multiple host controllers. A single host controller can connect up to 127 devices including hub devices. Hubs are used to link USB devices in series. The root hub is the hub that connects all USB devices. It is usually found in the host controller. One physical USB device can have several sub-devices, which are called device functions. Each function is assigned a single device address by the host.

It is important to protect users’ data from unauthorised access and use. One example is that user data and other confidential information can be stored on hard drives after they are removed from computers or storage systems. This could happen at the end of life. According to NIST 800-88, a federal standard, user data and other confidential information must be erased from storage systems. This is also required by Ponemon Institute document ‘Fourth Annual US Cost of Data Breach Study?, January 2009. Both documents are incorporated herein in their entirety.

These sanitization methods use non-destructive actions such as deleting files or blocking (such as formatting or overwriting externally dedicated software as required by DOD5220). Other techniques, however, use destructive techniques such as disk drive degaussing and physical drive destruction. Disks are removed from disk drives using physical drive destruction. They are then broken up or ground into tiny pieces. Degaussers can be used to erase magnetic data from disk drives. They also create high-intensity magnetic fields that erase all magnetic records on a hard drive or magnetic tape. In-drive encryption with an encryption key is a non-destructive method. Hughes G., Coughlin TC.,?Tutorial Disk Drive Data Sanitization?, describes the different sanitization schemes and requirements for disk drives. (September 2006), Edelstein R. Converge Net Inc.?The Limitation of Software Based Hard Drive Sanitization? The Myth of a Legacy Technology September 2007, in Edelstein R. Converge Net Inc.?Data Loss Prevention – Managing the Final Stage Of the Data Life Cycle Model?A Perspective On Decommissioning Storage Technology? (May 2007), Hughes G. F. and Coughlin T. of Coughling Associates.?Disposal of Disk and Tape Data?, Co-published with the IEEE Computer and Reliability Societies. (IEEE Security & Privacy pg. 29-34, July/August 2009. These are all incorporated as complete documents for all purposes.

“Considering the above, it would be a significant advance in the art to provide an improved storage or networking security method and system that’s simple, secure, cost-effective and faithful, reliable, easy-to use or sanitize, and/or uses existing components, protocols and programs for better security and additional functionality, as well as a better user experience.

“An apparatus and method to improve the security of sending a message that contains a series of messages from sender to recipient over multiple paths on the Internet is described. Interposition relay servers act as link servers between sender and receiver and pass along data. Each of the IP addresses associated with the sender, recipient, and servers is an IP address. The method of sending the message includes the following steps: Associating each message with an intermediate server using an associating scheme; each message slice containing one message element, associating each slice with an intermediate server according a slicing schema, and then sending each message slice along with the IP address to the server that was associated with it. Each message can use a different slicing method and an entirely different associating system. A number of intermediate servers perform the steps of receiving and identifying the message slice, the IP address of recipient, and then sending the message slice to the recipient or another intermediate server. The recipient performs the steps of receiving and identifying multiple message slices and reconstructing at most part of the original message before it was partitioned by the sender.

The sender method steps can be preceded by the step to determine the number of message slice that will be used for message partitioning. Next, the step of splitting the message into the desired number of message segments. It is possible to choose random numbers for the number of message slices that are used in message partitioning. Steps in the sender method may include determining how many message elements are contained in each message slice used for message partitioning. Then, the steps of splitting the message into messages slices with the desired number of message element can be followed. Each message slice may contain the same number of message elements or a distinct number. Each message slice may contain a random number of message elements. A non-overlapping partitioning may be used to include all message elements in one message slice. An overlapping partitioning allows for multiple message elements to be included in different message slices.

The slicing scheme can be based either on sequential partitioning where message elements in one of the message slice follow each other the same way as in the original message or non-sequential division where message elements in one of the slice do not follow one an another as in the original message. Interval sequential partitioning is another option. This means that the message elements in one or several of the message slices can be separated by at most one element in the message.

Each message element may be a bit or nibble, or a byte, or a multibyte word. It may also represent a number, or a character. A sender method could be preceded by padding the message or padding one or several of the message slices following the partition. Partitioning may be based on the current date (or the current TOD) (Time-of-Day).

“The slicing plan or other information about the partitioning can be sent together with one or several of the message slices. Information about a message slice may be sent with another slice. The order in which the message slices are sent may be random or determined by the order of the first message element within each message slice.

The step of encrypting a message before partitioning may precede the method of the sender. Partitioning is performed on encrypted messages, and the steps of decrypting the reconstructed messages follow the steps at the receiver. The method of the sender could be preceded by encryption of at least one message slice after partition at the sender, or at an intermediate host. In this case, the intermediate server may send the message slice before the step of decrypting the message slice. The recipient may also be required to decrypt at least a portion of the message slices before reconstructing the message.

The intermediate servers could be located in different geographical locations such as different cities or states, or even different countries. The intermediate servers can further perform the steps of storing the message slices, the IP addresses of the sender and the recipients.

“The intermediate server method or sender may be preceded by the storage of a list consisting of a succession IP addresses that can be used as source IP addresses by the associating schema. An associating scheme may associate each packet with a message slice with one of the IP addresses on the list. Each message slice is associated to a unique source IP address. Associating schemes may associate a packet containing a message slice with all or part of the source IP addresses. Associating schemes may associate the source IP address with a succession of packets, including the message slices, either sequentially or randomly. The source IP addresses can be randomly selected from the list to be associated with the succession of packets including the message slices.

“The sender and the recipient or an intermediate server can be a separate device or part of a device and may include a memory and a processor that is configured by the memory to perform sender, recipient or intermediate server methods. The sender could be a part of the computer that originates the message. Or, it may be connected to receive the message from another computer via a network, such as an Intranet or LAN, which is commonly used within an enterprise or other business entity. Either the sender or receiver (or intermediate server) can be co-located with a router (e.g. NAT-enabled router), a gateway, or firewall (e.g. sharing an enclosure, an Internet link, a LAN connectivity, an IP address), and connected between a LAN or the Internet.

The intermediate servers can be dedicated servers or integrated with other servers (e.g. sharing an enclosure or an Internet connection, a LAN connector, an IP address or a processor), each having a distinct functionality such as a webserver, online gaming server or instant messaging server. The intermediate server may share an enclosure, an Internet address, an IP adress, a processor or a peripheral device with the other server as part of this integration. The intermediate servers can also share some or all of the communication between the sender and recipient (e.g., transfer of packets containing messages slices), based on either strict routing or LSRR. Or onion routing, such the Tor technique.

“Each of the intermediate servers can execute a method to relay a message from sender to recipient. Each sender and recipient have an IP (Internet Protocol). The intermediate server executes the following steps: receiving from the sender a package that includes the payload message and recipient IP addresses. Next, extracting the message and identifying it, then extracting the IP address of the packet and then sending the message to the recipient, or to an intermediate host. If part of the message has been encrypted, the method may also include the step to decrypt the message once it is received. The method could also include encryption of the message before it is sent.

“In one embodiment, the message is composed a succession message elements. The method executed by any or all of these intermediate servers further involves the steps of splitting the message into a plurality message slices. Each message slice contains one or more message elements and each slice sends the IP address of its sender to the recipient, or to another intermediate server.

The method can be used to deliver audio or video information such as VoIP, video conference, IPTV, or Internet telephony services. The associating or slicing scheme can be random and based upon a random number. This may be based either on a physical process, or an algorithm to generate pseudo-random numbers.

“An intermediate server (or all of them) may continue to execute the steps of dividing the received message slice into a plurality sub-slices. Each sub-slice contains one or more message elements and then sending the subslices with IP addresses to the recipient to another intermediate or recipient server.”

The sender and recipient steps can be executed by either a separate software module or integrated with an application that generated the message or used it to generate the message. A single software module, or the same hardware, may be used as the sender or intermediate server. In this case the sender steps or intermediate server steps are executed by one software module or executed simultaneously by the same processor. A single software module, or the same hardware, may be used as the recipient or intermediate server. In this case, the recipient steps and intermediate server steps are executed by the same software module and executed by the exact same processor.

The sender may determine the slicing and associating schemes. Alternatively, the sender may decide the sender method. In either case, the sending step may include the receiving and storing of the slicing plan. The associating and slicing schemes may be sent via the Internet to the recipient. They can also be sent from one of the intermediate server or another server. The associating and slicing schemes may be periodically received at random, based on a date, or based upon TOD. One method of storing a message is to slicing.

A CAPTCHA can be used to increase communication security. You can add, integrate, embed, or even a portion of the CAPTCHA into a message, or a message slice. One example is that the message, or part thereof, may be embedded within a CAPTCHA. For example, it could use the characters from a message (or message slice) to generate a CAPTCHA image. Another example is that the CAPTCHA contains part or all the information necessary to decrypt the message or slice received. Information about the key public or private used to decrypt the message may be included in a CAPTCHA. One example is that the CAPTCHA might include information about the slicing algorithm or any other information involved in the reconstruction of the message.

“In one aspect, scrambling and descrambling schemes can be used to encrypt and decrypt digital data written onto a memory or storage (or both). The storage (or memory) physical means can be electrostatic, magnetic, acoustic or optical. It may be semiconductor (a.k.a. The memory may be semiconductor (a.k.a. The memory can be either volatile or non-volatile and may be static or dynamic. You can write the memory more than once or as part of the manufacturing process, or later (e.g. The memory can be written by the user using a specific equipment or as part a normal operation. Random or sequential access may be used. The memory can be file-addressable, location-addressable, or content-addressable. A non-removable media or a removable medium may be used. Access to a memory can be made via a bus or parallel connection. It may also be powered by a dedicated connection. Memory is often characterized by its access time and capacity. It can also be portable or enclosed in an enclosure. It could be a DAS or a part of NAS, SAN or SAN.

A bus can be used for any connection, including the connection of peripherals and memory to a processor. Buses can also be considered communication links (e.g. Ethernet or any other LAN/PAN/WAN communication links. Buses can be internal buses, external buses or both. Buses can be parallel or bit-serial. Buses can be built on one or multiple serial links, or lanes. A bus medium can be electrically conductor-based, such as wires and cables, or it may be based upon a fiberoptic cable. A bus topology can be point-to-point or multi-drop (electrical paralel) and may also include a daisy-chain. It may also use hubs and switches. Point-to-point buses can be either full-duplex or half-duplex. A bus can also be built using proprietary specifications or may be substantially or fully compliant with an industry standard (or any variation thereof). It may also be hot-pluggable. A bus can be designed to carry digital data signals only, or it may also carry power signals (commonly DC voltages), in separate and dedicated cables or connectors. Or, the bus may carry both power and digital data over one cable. Buses can be configured to support master/slave. Buses may have a separate timing signal, or self-clocking line code.

“In one aspect, a memory scrambler that connects between a processor (directly or via bus) and the address word (directly or via bus) is disclosed. Addressing the memory converts an address word to another according to a conversion scheme. This scheme may include a one-to-1 mapping scheme. A data scrambler can also be connected between a processor (directly or via bus) and the memory (directly or via bus). The data scrambler converts data words to be written to the memory according to a conversion schema, which could be a one to-one mapping scheme. In order to reconstruct the original word, an inverse conversion scheme can be applied to data words read from the memory. Each of the data or address scramblers can be connected-based. This means that the significance of each address or data bit in the address, or data words is altered. Any combination of logic may be used to create the data or address scramblers. This could be using discrete logic gates, ASICs and PLDs as well as memory, processors and any combination thereof. The memory can be either non-removable, or removable. In this case, the written information is scrambled using address or data scrambling. It cannot be read without going through the appropriate de-scrambling process.

“The scrambling scheme, or any of the scramblers, may be programmed once and then reset again. This could happen in manufacturing or by the user who uses a dedicated programer or on-board programming during system operation. Alternatively or in addition, the scrambling scheme may be field changed and overwritten/programmable in the field, such as by the processor accessing the memory. The scramblers can be volatile or nonvolatile. One scrambler (or both) could include a random generator. This generator is used to write random numbers in certain parts of the memory such as during write cycles.

Both address and data scramblers can be used simultaneously to access the same memory. The scrambler can use the same, similar, or different scrambling strategies, handle the same or differing bus widths, or be based on different implementations or component types. Two scramblers can be combined to share an enclosure, mechanical support and connectors. Power sources, interfaces, and power sources may also be shared. If the address word, data word, or both are carried using bit-serial connections or communications such as serial buses, the address or data word is first extracted from the processor. The address or data word is then identified and converted and then inserted into the serial stream connected with the memory. Converting the serial address or data word to parallel, converting it to another parallel address word (or data word) according to a conversion schema, then serializing and combining the parallel converted words over the bit-serial communication.

An adapter can include a data scrambler or address scrambler or both. It also may have encryption and interfaces that allow for connection to the processor (directly, via a bus, or via a bus). Passive or active electronic circuits may be included in the adapter or any portion thereof. The adapter or any part of it may be powered by the power source (AC, DC), or the power supply that powers the processor, or from the power sources (AC, DC), or the power supply that powers the memory, or both. Alternately, the adapter or any part thereof may be powered by a separate power source or supply. Alternately, the adapter or any part thereof may be powered by the bus or another connection to the processor. The connection or bus may also power the memory. Alternately, the adapter can be powered by a separate power source or supply. Alternately, the adapter can be powered by the bus or another connection to the memory. It may also power the processor directly via the connection or bus. A dedicated cable may be used to power the adapter via a connection (such a connector or bus), where it has power-dedicated wires/conductors, or by using power/data carried over the same wires as FDM or the phantom scheme. FDM adapters include circuits that split the power and data signals. These circuits may include a power-pass filter which substantially passes the power signal while substantially stopping it, or a data-passing filter which substantially passes the data signal while substantially stopping its power signal. Alternately, the capacitor may be connected to a transformer centre-tap for seperating power and data signals. Two transformers can be used in phantom schemes. They pass the data signal or signals between the primary windings and the transformers. The power is accessed at their center-taps. An adapter can use a separate power connector to receive power, or a connector that connects to a cable (such a bus cable) carrying both data and power over the same cable.

The adapter (or any portion thereof) can be used to supply power for a device connected to it such as a memory. This powering can be done via a connection or bus that uses a dedicated cable or using the same cable with power-dedicated wires and conductors. Or by using power and data over the same wires like FDM or Phantom scheme. FDM adapters include circuits that combine power and data signals. For example, a power-passing filters substantially pass the power signal while substantially stopping it, or a power-passing and data-passing filter working together substantially passing the data signal while substantially stopping its power signal. A capacitor may also be connected to a transformer centre-tap for power and data signal combining. Two transformers can be used in phantom schemes. They pass the data signal (or signals), between the primary windings and the transformers. The power is supplied at their center-taps.

“Adapters can be manufactured or provided where each one contains a unique address scrambling scheme or distinct data scrambling system, or both.” Alternately, adapters can be manufactured in pairs or with other groups that share the same scrambling scheme.

An adapter, an address/data scrambler or any part thereof can be implemented using software, firmware, hardware or a combination. Hardware can be a separate physical entity. It could take the form of a chip, an IC or a box-shaped enclosure. A PCB may also carry ICs and other electronic parts (such as plug-ins or removable modules). Alternately, or in addition to the above, circuits and functionalities can be integrated with a processor or a memory, or an intermediate device such as a hub, switch or router, or bus expander. If the physical entity is separate, the electrical connections may use standard expansion connectors or bus connectors, as well as edge connectors. Each connection can be keyed, and it is recommended that hot-plugging is supported.

One aspect of the invention is an adapter that connects to a processor and to an address-addressable storage device capable of storing data in an address space. The adapter can be connected to the processor via a bus that is first-type. It may include a first port connecting to a primary bus; a first interface coupled with the first port to receive a first data message associated with an address within the address space; a secondary port connectable with a secondary bus; a third interface coupled with the second port to transmit a second data phrase associated with the address; and a scrambler connecting between the first interface and the second interface for converting the first word to the memory.

“In one embodiment, an adapter is disclosed for connecting to a processor as well as to a memory (such location-addressable memories) with an address space. The bus of the first type connects the memory to a processor. The adapter comprises a first port that connects to a first bus type for connecting the processor to the memory; an interface coupled to this first port to receive a first address from the processor; another interface coupled with the second bus to connect to the memory; a third port that connects to a fourth bus for connecting the memory to the processor; and a third interface coupled to second port to transmit a second address from the address space to memory. A scrambler is connected between the first interface and the second interface to convert the first to a different from the first to a new address word. The scrambler can only be used to convert the first address word to the second. Each of the first and last address words can define a sequence, so the conversion may involve rearranging at least two bits in the address words. Each of the first or second address words can contain multiple bits. A level of significance could be assigned to each bit. The conversion may also include changing the significance of at least two address words.

The scrambler could be based upon logic gates that implement a Boolean function such as PLD memory, discretely packaged logic gates or PLD logic gates. The processor may program the conversion to follow a pre-set scheme. For the processor to address, the scrambler can be connected to the first bus. The second bus type can be the same as the first, or it may be a different type. The memory can be included in the adapter. It may be electrostatic, magnetic, magnetic, acoustic or optical. The memory can be file-addressable and content-addressable. It may also be part of a NAS, SAN, or both. The memory can be once-written and connectable to the processor for reading from or writing to via the second bus. This bus could be either a parallel bus, bit-serial, or both.

“The adapter could include a power supply with a power port that can be powered by a power source. The power supply may have one or more DC outputs to power at least a portion of the memory. An adapter could include a power connector to connect to the power source. The power port can be coupled to this power connector. The second bus could be built on a cable carrying power signals. The adapter may also include a bus connector to connect to the cable.

The memory can be random-accessed or sequentially accessed. It may also be location-based and randomly-accessed. Multiple times can be written to it. The memory can be volatile and may be based on semiconductor storage medium such as RAM, SRAM or DRAM. Non-volatile memory can be based on semiconductor storage medium such as RAM, PROM or EPROM. It may also be Flash-based such as SSD drive, USB?Thumb? drive. Non-volatile magnetic storage media, such as HDD, may be used to store the memory. An optical storage medium, which can be recordable and removable, may be used to store the memory. This may include an optical drive. You can store the media on CD-RW or DVD-RW. An adapter, memory, or both, may be an IC or a PCB with one or more ICs mounted on it, or a box-shaped enclosure.

“The adapter could also include an encryptor/decryptor function that uses an encryption scheme that is coupled to the first and the second interfaces. This allows for the decryption and encryption of digital data between these buses. AES 128, 192, or 256 bits may be used as the encryption scheme.

The first and second buses (or both) can be based on either a PAN or a networked communication link. Either the first or second bus, or both, may be based upon Ethernet. They may also be substantially compliant to IEEE 802.3 standards. Each bus, or both, may be based on either a multi-drop or a daisy chain topology. They may also use half-duplex and full-duplex connections. Each bus may be wired-based, bit-serial, point-to?point and wired-based. A timing, clocking, or strobing signal can be carried over dedicated wires or used in a self-clocking system. The bus medium may be a fiberoptic cable. An adapter may also include a connector to connect to the fiberoptic cable.

Each bus (or both) might use conductors such a bus cable with multiple wires. The adapter may also include a connector to connect to the bus cable. One or more DC, or other power signals may be carried by the bus cable over dedicated wires. Or the same wires that carry the digital data. An adapter could consist of a power/data splitter arrangement with first, second, and third ports. Only the digital data signal is transmitted between the first two ports and only the power signal between the third and fourth ports. The first port is connected to the bus connector. FDM may be used to carry the digital and power signals. The digital data signal is transmitted over a frequency band that is higher than the power signal. A power/data splitter could include an HPF connected between the first two ports and a LPF between the third and fourth ports or a transformer with a capacitor connected between the windings of the transformer. The power and digital signals can be carried in phantom scheme substantially following IEEE 802.3af/2003 or IEEE 802.3at/2009 standards. At least two transformers may be connected to the transformer windings.

The adapter may supply at least a portion of one or more power signals that are DC type and carried over dedicated wires, or carried over the same wires carrying data. An adapter could be a power/data combination arrangement with first, second, and third ports. Only the digital data signal is transmitted between the first two ports and only the power signal between them. The first port is connected to the bus connector. FDM may be used to carry the power and digital signals. The digital data signal is transmitted over a frequency band that is higher than the power signal. A power/data combiner could include an HPF between first and second ports, and a LPF among the first and third port. A transformer and capacitor may be connected to the transformer windings. A phantom scheme may be used to carry power and digital data signals substantially in accordance with IEEE 802.3at/2009 standards. The power/data combiner could include at least two transformers with a center tap connection.

The adapter can be implemented as a separate physical entity such as a die or an IC. A box-shaped enclosure or a PCB carrying ICs or other electronic components. A plug-in card, or a removable enclosure may also be used. The adapter can be integrated with or integrated with the processor.

Each bus may be built on a cable. The connector that connects to the cable may be the first or second port. The cable can be made of conductive wires, or a fiber-optic one. The connector can be used to connect the first and second interfaces. These interfaces allow for both transmitting and receiving data from the cable. The transmitter can use differential signaling, emphasis molding, or self-clocking code. It may also employ error detection and alignment, clock-correction, or channel-bonding. The receiver can use equalization, impedance match termination, or PLL. It may also use decoding and detecting encoded-based errors. The adapter may include a serializer/de-serializer that is coupled between the first interface of the scrambler. This allows for parallel conversion of digital data from the first interface to serialize digital data from the scrambler. The second bus may be a serial bus, and wherein the adapter further comprises a serializer/de-serializer coupled between the second interface and the scrambler, for converting to parallel the digital data received from the second interface and for serializing the digital data received from the scrambler.”

The adapter can be integrated with the memory or the processor, and may include a component that is shared with the memory or processor. The adapter could be a single enclosure that houses the first and third ports, the first interfaces, and the scrambler. It may also include the enclosure housing the processor or memory. An adapter could include a power supply to power at least a portion of it, as well as the power supply being connected to power the processor and memory. The adapter could contain components that are mounted on a substrate, such as a PCB. The substrate can be used to support the processor and memory.

“In one aspect, it is disclosed that a set of two or three adapters is disclosed. Both adapters use scramblers with the same scrambling scheme. The adapters can be mechanically attached, detachable, or both. An adapter can be a plug-in or removable unit that includes the memory and/or the processor. DRM is a method of allowing access to or authentication to scrambled software.

Information is stored in multiple memory locations for one aspect. The information can be split into multiple parts stored in multiple memories. Splitting can be address-based, data-based (such as data word), or both. The required address space is an overlapping or non-overlapping division between the memories. Each address is associated with a memory (or multiple addresses) using a mapping scheme. The mapping can be either sequential or not. Alternately, or in addition to the above mentioned options, the data word may be split using a mapping scheme between the memories. Random data may be used to fill in locations not being used.

The above summary does not cover all aspects of the invention. In fact, the inventor believes that his invention encompasses all possible combinations and derivatives of all aspects listed above. These combinations offer particular benefits that are not specifically mentioned in the summary.

“The principles and operation for an apparatus according the invention can be understood by reference to the drawings and the accompanying description. Similar components appearing in different figures will be denoted with identical reference numerals. These drawings and descriptions are purely conceptual. In practice, one component may implement several functions. Alternately, each function could be implemented by multiple components or devices. The figures and descriptions use identical reference numerals to indicate components that are common to multiple configurations or embodiments. Even if a different suffix is used, identical numerical references refer to functions and actual devices that are identical, substantially the same, or have similar functionality. The components of the invention as described and illustrated in these figures can be assembled and designed in many different ways. The following description of the various embodiments of apparatus, system and method of this invention as illustrated in the figures is not intended as limiting the scope of the invention as claimed. It is only representative of possible embodiments of it.

“In one aspect, a message that will be sent via the Internet is first cut into one or more pieces (?slices?) Each message slice is combined together with the ultimate destination address and slicing data. A modified message that contains the message slice and the ultimate destination address, is sent in one or more packets via the Internet to a relay server. This server is not always associated with the ultimate destination device. The relay server can then identify the ultimate destination, forward the message slice to it (with the source address in the packets), or send it to another relay server which will continue the process.

“In one example, the laptop 12a (?sender?) The laptop 12 a (?sender?) wishes to send a message on the desktop computer 13c (?receiver?) or ?recipient?) via the Internet 11 shown in FIG. 2 above. The credit card number?918283746547 is used to make a commercial commerce transaction. The credit card number must be exchanged between the client who purchased laptop 12a and the customer who purchased store desktop computer 13c. Slice #3 consists of?6547′. The slice #1 is combined with the destination IP address 13 c and the number 1?. The slice #1 is used to identify the slice and is sent as a regular package to the server 14b, which acts as a relay server. As shown in FIG. 30, system 30 shows an example. FIG. 3a shows an example of this. or ?recipient?) The payload of packets is not encrypted with the destination address. The relay server 14b receives packets from source laptop 12a. It decodes destination address from packets payload and adds it to the message. If necessary, it sends the newly formed message over the Internet to destination computer 13c. The packets could use, for example, the 31 c and 31 d routes, 31.e and 31.f paths over the respective communication link 17 f,16 g,16 h, and 17 c. This forms a communication path between the server 14 b and the destination 13 c via routers 15 15 i, 15 d and 15 d as shown in FIG. 3 a.”

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Write down a brief, but precise description of the invention. Don’t use generic terms such as “device”, “process,” or “system”. Consider synonyms for the terms you chose initially. Next, take note of important technical terms as well as keywords.

Use the questions below to help you identify keywords or concepts.

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2. These terms will allow you to search for relevant Cooperative Patent Classifications at Classification Search Tool. If you are unable to find the right classification for your invention, scan through the classification’s class Schemas (class schedules) and try again. If you don’t get any results from the Classification Text Search, you might consider substituting your words to describe your invention with synonyms.

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5. This selection of patent publications is the best to look at for any similarities to your invention. Pay attention to the claims and specification. Refer to the applicant and patent examiner for additional patents.

6. You can retrieve published patent applications that match the CPC classification you chose in Step 3. You can also use the same search strategy that you used in Step 4 to narrow your search results to only the most relevant patent applications by reviewing the abstracts and representative drawings for each page. Next, examine all published patent applications carefully, paying special attention to the claims, and other drawings.

7. You can search for additional US patent publications by keyword searching in AppFT or PatFT databases, as well as classification searching of patents not from the United States per below. Also, you can use web search engines to search non-patent literature disclosures about inventions. Here are some examples:

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