SAMSUNG ELECTRONICS CO., LTD. (Suwon-si, KR)
The examples of the disclosure pertain to the semiconductor stack where upper chips are attached to a carrier wafer and an upper lateral-side passivation layer can be placed on the sides of the upper chips and between adjacentones of the upper chips, thereby being capable of controlling the wafer bonding interface and achieving redistribution of upper chips, and protecting against degradation of the bonding yield. Examples of embodiments comprise a process for manufacturing thesemiconductor stack.
2. Description of the Related Art
An upper wafer and lower wafer are joined in the traditional wafer-to-wafer (W2W) bonding. They have the same size chip, the same arrangement and share the same wafer. This can lead to degradation in the yield of rolled throughput following bonding. In the event that any of the die on the upper wafer or the die that is on the lower wafer are defective or defective, a stack of semiconductors placed at a position corresponding to the defective die upon bonding on wafers could be damaged. If die-to-wafer (D2 W) technology is used in order to avoid such accumulation of failure it is the only way KGDs are sorted out from the chips of the upper wafer, and later be joined to the lower. However, in this situation, there may be a problem in that process the stability of fine pitch can be degraded. In addition, adhesive is utilized to connect chips during D2W collective bonding takes place. In this scenario an interface that is flat could not be created due to an adhesive’s height difference even when chips are alike. Technology that increases yield and efficiency in wafer bonding is thus desirable.
A few examples of the disclosure offer an electronic stack in which only the upper chips with no defects are sorted and attached to a carrier wafer. A higher passivation layer that is located on the sides of the upper chips, and also between the adjacent ones of the upper chips, thereby being able to control the bonding interface to be flat and increasing the yield of rolled throughput thereof, and an approach to manufacturing the semiconductor stack.
Some exemplary embodiments of the disclosure also include an electronic stack where the gap between adjacent upper chips is filled with an upper lateral-side passivation layer, as well as bonding pads as well as a bonding passivation layer are fabricated on the upper surface of the resultant structure through a redistribution layer formation process or the like, thereby being capable of creating hetero bonds between various types of chips. It also includes an adhesive pad within the gap between adjacent ones of the upper chips as well as a method to fabricate the semiconductor stack.
Additionally, certain exemplary embodiments of the disclosed invention provide the semiconductor stack with the carrier wafer and cutting interfaces for wafers which is capable of performing sophisticated cutting or stealth cutting of the wafer carrier while reducing the use of an adhesive upon attaching an upper chip to the carrier wafer, thus enabling a desired process to be accomplished at a higher temperature and a method of manufacturing the semiconductor stack.
A preferred example of the disclosure describes the semiconductor stack which includes a lower chip, an above-the-lower chip chip, an over-the-upper chip and an upper lateral side passivation layer that covers the upper chip’s side and a series of bonding pads, as well as layer of bonding passivation between the lower and upper chips.
A semiconductor stack as per an embodiment of the disclosure can comprise a primary chip, a second chip disposed over the first chip, a first lateral-side passivation layer that covers a side of the second chip, a plurality of firstbonding pads, and a bonding passivation layer disposed between the first chip and second chip and a third chip that is disposed on top of the second chip, the second layer of lateral-side passivation that covers a portion of the third chip and a number of bonding pads as well as an additional bonding passivation layer disposed between the second chip and the third chip.
A semiconductor stack according to an embodiment of the disclosure can comprise one chip, a second chip and a fourth chip that are stacked one on top of the other and an initial lateral-side passivation that surrounds a side of the second chip, aplurality of first bonding pads , a first bonding passivation layer placed between the first chip and the second chip as well as an additional lateral-side passivation layer covering a side of the first lateral-side passivation layer that surrounds the side face of the second chip, side surfaces of the first layer of bonding passivation as well as a side surface of the first chip.
In accordance with various embodiments of disclosure according to various embodiments of disclosure, the semiconductor stack comprised of only the top chips that are free of defects. The upper lateral-side passivation layers are placed at the side surfaces of the top chips, and filled between the adjacent lower chips. This results in an easier wafer bonding interface and a greater roll throughput yield. In addition, aredistribution layers can be carried out on the upper surfaces of the upper chips , and this means that hetero bonding between different kinds of chips may be possible. Furthermore, disposition of bonding pads may be extended to create a gap area betweenadjacent ones of the upper chips.
Furthermore the method of making a semiconductor stack accordance with various exemplary embodiments of the disclosed method, a carrier wafer, which includes a wafer cutting interface for stealth cutting or smart cutting, is employed. as such, it may be possible to eliminate use of adhesives upon attaching an upper chip to the carrier wafer, thereby making it possible for a desired process be performed at the higher temperature.Click here to view the patent on USPTO website.
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