SAMSUNG ELECTRONICS CO., LTD. (Gyeonggi-Do, KR)
What is a Patent for Semiconductor packages with stiffening structures
Search Patent for Semiconductor packages with stiffening structures
1. Field
A few examples of the disclosure concern semiconductor packages, including memory chips and logic chips, and a stiffening mechanism, installed in an interposer.
2. Description of the Related Art
A semiconductor package , which includes a logic device and high-bandwidth memory (HBM), is being studied for the next generation of high-performance communication devices. These packages of semiconductors could comprise an interposer that is mounted on a substrate, and an intelligence chip with plurality memory stacks mounted over the interposer. Particularly, the semiconductors that are suitable for mobile communications are specifically created to be slim. They may also be vulnerable to external physical stresses like warpage. Additionally, warpage of chips can easily happen in the an extension direction along boundaries (or boundaries) of the chips. The resulting semiconductor package may be electrically or physically damaged in this scenario.
Some examples of disclosure are packages that have a stiffening structure that can limit or prevent warpage.
Some example embodiments of the disclosure also include stiffening structures that protect constituent elements from physical impact.
The various problems that need to be resolved by various embodiments of the disclosure will be described in the specification.
A specific embodiment of the disclosure is a semiconductor package that includes a substrate, interposer in the substrate, as well as two logic chip. The first and second logic chips are placed side-by-side to allow for proximity between them. Memory stacks comprise memory stacks that have a number of memory chips. Each memory stack is situated next to the one that is corresponding to first and second logic chips. Memory stacks are placed sit on the interposer as well as the stiffening chip in between the memory stacks. The stiffening chip aligned to the line between the first and two logic chips and the two logic chips.
A semiconductor package according to certain examples of the disclosure may include a substrate, an interposer mounted on the substrate, first and second logic chips in the interposer so that the second and first logic chips are located adjacent each other first memory stacks on opposite side surfaces of the first logic chip and second memory stacks located on opposite side surfaces of the second logic chip, and stiffening chips in between the first memory stacks and the second stacks of memory. The firstand second logic chips may be electrically connected by wiring within the interposer. The minimum distance between first and second logic chips could be less than the distance between the first and second memory stacks. The stiffening chips might be adjacent to a boundary area between the first and second logic chip. They may also be aligned to an extension line in the boundary area. The boundary may be greater than the stiffening chips.
A semiconductor package in accordance with specific examples of the disclosure could comprise a substrate, an interposer on the substrate a plurality of logic chips within the interposer, adjacent to each other within a 100mm, and the logic chips are electrically connected by the interposer a plurality of memory stacks on the interposer, and each of which includes an array of memory chips, as well as through vias running vertically through the memory chips, as well as a plurality ofstiffening chips that are placed on the interposer. Longer sides of stiffening chips are parallel to shorter sides of the memory stacks, smaller sides of the stiffening chips have the length of 1/2 or less of the length of longer sides of the memory stacks, and each of the stiffening chip’s sides has a greater width than a boundary between the corresponding chips of the logic chips, so that the stiffening chips horizontally overlap with portions of the corresponding logic chips and molding compoundsurrounding side surfaces of the interposer side surface of the logic chips side surfaces of the memory stacks and side surfaces of the stiffening chips.
Various effects according to example embodiments of the disclosure will be described in the specification.
Click here to view the patent on USPTO website.
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