Software Technology for Package substrate and method for manufacturing the package substrate, as well as semiconductor package that includes the package substrate as well as method of manufacturing the semiconductor package

Samsung Electronics Co., Ltd. (Gyeonggi-do, KR)

A package substrate can comprise first conductive patterns as well as a first and second insulation layers. A semiconductor chip may be utilized to connect the first pattern with an electrical circuit. The first patterns with conductive properties may have an insulation layer covering its sides and upper surfaces. A minimum of one opening could be located under the initial insulation layer. The second insulation layer could be situated on the lower surface of the first conductive pattern. The opening could allow gas from the DAF to escape easily. The spreading of cracks, which can be generated between the the molding member for the semiconductor chip and the chip toward the conductive patterns on the substrate of the package may be slowed or stopped. The molding component and the semiconductor chip can be strengthened to improve adhesion.

1. Field

Examples of embodiments include a package substrate and method of manufacturing it, and the semiconductor package, which includes an approach to manufacturing the substrate for packaging. Particularly, the examples refer to a packagesubstrate that is utilized in a semiconductor packaging process as well as a method of manufacturing the packaging substrate.

2. Description of Related Art

Generally, a semiconductor package may include an package substrate, a semiconductor chip, an electrical wire, and a molding member. Die attach films (DAF) may be used to secure the semiconductor chip to the upper layer of a package substrate. The package substrate could also be used for connecting the wire with conductive. The molding component may be formed on the top of the substrate in order to protect the semiconductor chip as well as the conductive wire. Package substrates can comprise an insulation layer and the conductive pattern. are positioned on the lower and upper surfaces of the pattern that conducts electricity.

According to related arts, during a process for connecting the semiconductor chip to the package substrate using the DAF and/or a process for making the mold member, a liquid comprising an inflammable material could be discharged through the DAF. The gas could cause a void to form at one portion of the mold member close to a side area of the chip to weaken an adhesion force between the chip and the molding.

The semiconductor device can be exposed to high and extremely low temperatures as well as high humidity in order to guarantee reliability. The strain generated during the test may be concentrated on an interface between the semiconductor chip’s face and the molding member which could cause cracking or delamination. Particularly, the gap in the interface between the semiconductor chip and the molding member can cause the delamination process and/or crack. In order to result in damage to the package substrate the crack could extend to the package substrate.

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