Software Technology for Multi-chip package containing the same packaging substrate

SAMSUNG ELECTRO-MECHANICS CO., LTD. (Suwon-si, KR)

A package substrate, including an underlying substrate, a second structure disposed on the substrate and featuring a first through-portion, a wire layer disposed in the first through-portion of the substrate, a first insulating layer placed in the first through-portion of the substrate and that covers at least a portion of the first wiring layer and a second wiring layer disposed on the first insulating layer and a multi-chip packaging that includes the package substrate are included.

Comparable to a situation in where the entire system are made from one silicon die, a case that a die has been divided into chiplets could result in lower costs for manufacturing and lower disposal costs because of low yield. In the current trend of chiplets, technology for interconnecting chiplets have developed. A substrate that includes an interposer made of silicon or a substrate with a silicon-based connector bridge is possible to achieve die-to-die, or an electrical connection. These technologies are necessary for the production of costly silicon interconnects. In addition, in the case of a silicon-based interconnectbridge, a reliability issue arises due to a coefficient of thermal expansion (CTE) that is not in line with the silicon material of the bridge and the organic material of a substrate.

One aspect of the disclosure is to provide a package substrate, capable of providing a cheap multi-chip interconnection, and an integrated multi-chip package that includes the same.

The present disclosure also offers a package substrate that can lower the risk of yield reduction as well as a multichip package which contains the same.

Another aspect of the present disclosure is that it provides a package substrate, having an extremely wide range of flexibility in wiring design, and a multi-chip package including the same.

Another feature of the present disclosure is the provision of an improved package substrate that has better reliability, advantageous for bending control, and a multi-chip package that contains the same.

Another aspect of the present disclosure is to provide the possibility of a package substrate capable of creating a compact structure and an integrated multi-chip package that contains the same.

According to an aspect of the present disclosure, a fine circuit can be constructed by forming an elongated dam-shaped structure over an object and then sequentially creating a wiring layer as well as an insulating layer and so on, in a through-portion provided throughthe structure.

For example, a package substrate is the substrate, a first structure that is placed on the substrate, and comprising one through-portion, the first wiring layer that is disposed in the first through-portion on the substrate as well as a first insulating layers placed in the first through-portion of the substrate, and covering at least a part of the first wiring layer and another wiring layer that is disposed on the first insulating layer.

A multi-chip device includes a substrate including a substrate, the first structure is placed on the substrate with an initial through-portion and a first wiring layer located in the first through-portion of the substrate, afirst insulating layer disposed in the first through-portion on the substrate and covers at least a part of the first wiring layer, and an additional wiring layer placed on the first insulating layer a first semiconductor chip disposed on the package substrate and having first connection pads, and a second semiconductor chip disposed around the semiconductor chip on the package substrate and with second connection pads. Through the first wiring layer, at least one of the second and first connection pads is connected electrically to the other.

For example, a package substrate may include the substrate with a dam-shaped structure that is disposed on the substrate initial patterns that are disposed inside the dam-shaped structure and on the substrate second patterns disposed outside the dam-shaped structure andon the substrate and an insulating layer that covers only the first pattern between the first patterns and second patterns as well as a wiring layer on the first layer of insulation, and a via layer disposed in the first layer of insulation and connecting thefirst patterns to the wiring layer.

Click here to view the patent on USPTO website.

 

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