A device is disclosed. A buffer may be included within the device to receive the message with a low bitwidth. A reconstruction circuit might use a reconstruction function to the first low-bit width message to generate a first high-bit width message. A computing circuit may apply a computation function to the first high-bitwidth message to generate a second high-bit width message. A quantization circuit might apply a quantization function to a second high bitwidth message to produce a second low-bit width message. A decision buffer may keep the second low bit width message. The reconstruction function as well as the quantization function may vary depending on an iteration and an element of the device.

It can be difficult to assess the information bits stored in storage devices that are encoded by codewords. This is referred to as decoding. Decoding circuits that are specifically designed for this purpose may use resources that might be better utilized for different purposes.But when resources are limited to a decoder’s circuit, the performance of a decoder may be diminished, that is, the decoder could take longer time to calculate, which can cause other processes to slow down in the storage device that could be dependent on codewords.Limited resources allocated to decoding may also result in the decoder inaccurately estimating the original information bits: i.e., more errors in decoding.

There is a need to understand information faster and more precisely without the need for substantial additional resources.

The drawings described below are illustrations of ways in which embodiments of the disclosure could be implemented and are not intended to limit the embodiments of the disclosure. Specific embodiments of the disclosure may include elements not shown inparticular figures and/or may omit certain elements in particular images. Illustrations are intended for illustration purposes only and are not scaled.

FIG. 1 shows a system including a storage device that may use a Reconstruction-Computation-Quantization (RCQ) approach in a Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoder, according to embodiments of the disclosure.

FIG. 2 illustrates the specifics of the machine in FIG. 1, according to embodiments of the disclosure.

FIG. 3 illustrates the details of the storage device shown in FIG. 1. If it is implemented as it is a Solid State Drive, (SSD), according embodiments of this disclosure.

FIG. 4 illustrates the general arrangement of a QC-LDPC code within the SSD of FIG. 3. Based on the embodiments of this disclosure.

FIG. FIG. 5. illustrates the general layout for the RCQ approach within the QC-LDPC Code in the SSD. 3, according to examples of the disclosure.

FIG. 6 illustrates an architecture of the decoder shown in FIG. 4, according to the embodiment of the disclosure.

FIG. 7 illustrates the memory in FIG. 6 Quantization and reconstruction tables, according to one embodiment of the disclosure.

FIG. 8 illustrates a graph that compares error rates using the decoder of FIG. 4 with other decoders.

FIG. 9 displays a graph showing the average iteration time using the decoder in FIG. 4 with other decoders.

FIGS. 10A-10B depict a flowchart of an example method for using the decoder from FIG. 6, according to embodiments of the disclosure.

Examples of the disclosure are a Low-Density Parity-Check (LDPC) decoder. The LDPC decoder may use a Reconstruction-Computation-Quantization (RCQ) approach, with each layer in the decoder potentially implementing different reconstructionand quantization functions. This way, better decoder performance may be achieved.

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