A silicon carbide wafer that has improved performance using direct application interconnects with conductive properties that are placed on printing connection pads. The interconnected conductive ink can be routed to create an individual length resistive trace to be used on a device after fabrication and testing of the device.

1. Field of the Invention

The invention is about improvements to wafer-based conductive interconnects. Particularly, the invention relates to enhancements that are specifically suited to simplify customization and reduce processing in wafer circuit manufacturing. This invention is specifically concerned with interconnect pads that allow microprinting of conductors and electrical trace.

2. Description of the Known Art

Inks that are electrically conductive can be found in numerous varieties, and so can the proficient in the art of. The following patents offer details about conductive inks:

U.S. Pat. No. 9,899,298, granted to Vincent, et al. On February 20, 2018, Vincent and co. received the abstract below: Microelectronic packaging having mold-embedded trace and methods of manufacturing. The abstract reads as follows: Methods for fabricating microelectronicpackages, such as Fan-Out Wafer Level Packages, and microelectronic packages are provided. In one embodiment, the method includes placing a first semiconductor die on a temporary substrate, forming an electrically-conducive trace in contact with atleast one of the first semiconductor die and the temporary substrate, and encapsulating the first semiconductor die and the electrically-conductive trace within a molded panel. The temporary substrate is removed to reveal a frontside of the molded panelthrough which the electrically-conducive trace is at least partially exposed. At least one redistribution layer is formed over the frontside of the molded panel, the at least one redistribution layer comprises an interconnect line in ohmic contact withthe electrically-conducive trace.

U.S. Pat. No. No. 7,952,107, issued by Daniels, et. al. on May 31, 2011. called Solid state light sheet and encapsulated bare die semiconductor circuits with electrical insulation. The patent says that at least one of the first substrates may be a flexible material such as PET, PEN or Kapton polycarbonate, vinyl or. A printed conductive ink can be used to create at the very least one of the first, third, and fourth wiring lines. This includes gravure, inkjet or electrostatic printing.

U.S. Pat. is another patent. No. 9,803,098, issued to Cho, et al. 9,803,098 issued to Cho and Cho. No. 9,631,106, issued to Maaninen, et al. April. 25/2017, entitled Conductive ink conductor U.S. Patent. No.9,123,705 issued to Blanchard, et al. on Sep. 1, 2015. It was titled Conductive ink for filling vias; and U.S. Patent. No. No. 7,806,974 was issued by Hwang, et.al. in October. 5, 2010, entitled highly conductive ink composition, and method for creating a metalconductive pattern.

Each of the patents mentioned is hereby expressly incorporated into the entirety of them by reference.

From these prior references it is apparent that the patents in prior art are extremely limited in their use and instruction and a better direct application ink-conductive interconnect wafer is needed to overcome these limitations.

The present invention is directed to an improved wafer using direct application of conductive ink interconnects placed on printing connection pads. A resistive trace is printed by a print connection pad as per an exemplary embodiment. In accordance with an exemplary embodiment of the invention the pad for printing is used to create an exemplary routing trace. You’ll be able to recognize these advantages and characteristics of the invention in the next description.

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