Apple Inc. (Cupertino, CA)

Certain embodiments enable enhanced accuracy of packets (PER) and signal-to-noise ratio (SNR) channels capacities, aggregated throughput, and communication distances in wireless communication networks. For instance, an electronic device has buffers that store a first descrambled bit estimate sequence. A encoder is also present in the electronic device. This encoder receives a descrambling order and generates an encrypted descrambling order. A multiplier circuit takes bits estimation sequences and an encoded unscrambling sequence and creates a second descrambled bits estimate sequence. The adder circuit is integrated into the electronic device that combines the first and second descrambled bit estimate sequences to generate a combined descrambledbit estimate sequence.


The described embodiments are generally related to improvement in the overall signal to noise ratio (SNR) and the extension of range in wireless communications.

Related Art

In wireless local area networks (WLANs) the maximum range can be restricted by the lowest Modulation and Coding Scheme (MCS) index value (e.g. MCS0) and/or the lowest value of the complementary code keying (CCK) modulation scheme (e.g. 1 Mbit/sec).MCS index values are combination of number of spatial streams as well as the type of modulation used and the rate at which they are encoded. Furthermore, due to the scrambling processes in transmitters in WLANs, the receivers in WLANs cannot make use of soft combing of multiple transmissions.The transmitting payloads of multiple transmissions received by the receiver is scrambled by different scrambling sequences. Even if the WLAN receiver is equipped with hybrid automated repeat requests (hybridARQ–HARQ) but it’s not possible for the receiver to combine several transmissions.

One embodiment comprises an electronic device, a technique, and a computer program application that uses HARQ as well as soft combing of several transmissions. Certain embodiments permit the possibility of altering the sequence in which descrambling or encoding is performed on receiver electronic devices. Also, the payloads of received frames are first descrambled before they are decoded,according to some embodiments. Through descrambling prior to decoding, the receiver electronic device can be able to mix payloads of multiple transmissions received at the device that is used as a receiver. Softly combining multiple transmissions may improve the packet error rate (PER) as well as the signal-to noise ratio (SNR) as well as channel capability as well as aggregated throughput and communication range. In certain embodiments, improvement in SNR can be translated into an extension of range of the communications system.

Some embodiments include an electronic device, method and computer program program that decodes headers (e.g., MAC headers) of received frames in initial stages of frame reception. The header information could be used to implement the HARQ and soft combining of several transmissions.

Certain embodiments are suitable for electronic devices. The electronic device includes buffers that store a first descrambled bit estimate sequence. A encoder is part of the electronic device, which can take a descrambling sequence and create an encoded descrambling order. The multiplier circuit has an encoder that receives a bit estimate sequence as well as the encoded descrambling sequence. The circuit is then able to generate an additional descrambled bits estimation sequence. The encoder can also contain forward error correction (FEC) encoder. A circuit for adding an adder is part of the electronic device that blends the descrambled first and second bits estimate sequences and a decoder which can decode the combined descrambled bit estimate sequence.

Certain embodiments pertain to electronic devices. The electronic device comprises a memory that stores program instruction and a first descrambled bits estimate sequence, and processor. The processor, upon executing the program instructions,receives a descrambling sequence and generates an encoded descrambling sequence. The processor further receives an estimate sequence for bit size and the descrambling sequence encoded and generates a second , descrambled bit estimate sequence. The processor determines that the second descrambled bit estimate sequence corresponds to an retransmission of the previous descrambled bit estimation sequence and following the determination, combines the first descrambled bit estimate sequence with the second descrambled bit estimate sequence. The processor decodes the combined descrambled bits estimate sequence.

Some embodiments relate to a method. The method involves receiving a descrambling order and generating an encrypted order. The method also involves the receipt of a bit estimation sequence as well as an encoded sequencing , and then the generation of a descrambled bit estimate sequence, based most in part on the bit estimate sequence as well as the descrambling sequence encoded. The method also includes determining if the first descrambled bits estimate sequence is a copy of a second descrambledbit estimate sequence. The method also includes the combination of the initial descrambled bits estimation sequence and the second descrambled bit estimate sequence. The method also involves the decoding of the descrambled bits estimate sequence.

This Summary is provided merely to illustrate some embodiments to provide an understanding of the topic covered in the disclosure. The above-described characteristics are only examples and are not to be construed to limit the scope or meaning of the matter covered in this disclosure. Other features, aspects and advantages of the disclosure will be evident from the detailed description as well as the Figures and Claims.

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