Software Technology for “3D semiconductor device, structure”

Nanotechnology – Zvi Or-Bach, Jin-Woo Han, Monolithic 3D Inc

Abstract for “3D semiconductor device, structure”

“A 3D device” includes a first and second levels that include logic circuits, a plurality dynamic memory cells and a third level with a plurality non-volatile memories cells. The device also has refresh circuits for refreshing the dynamic memory cells.

Background for “3D semiconductor device, structure”

“1. “1.

“This application relates generally to Integrated Circuit (IC), devices and fabrication techniques, but more specifically to multilayer (3D-Memory), devices and fabrication methodologies.”

“2. “2.

“In the last 40 years there has been a significant increase in the functionality and performance of Integrated Circuits. This is largely due to the phenomenon known as “scaling?” This refers to the fact that component sizes, such as lateral or vertical dimensions, within ICs have been decreased (?scaled?) Each successive generation of technology. Complementary Metal Oxide Semiconductor ICs have two main types of components: wires and transistors. Typically, transistor performance and density improve with?scaling”. This has led to the above-mentioned improvements in IC functionality and performance. With?scaling?, however, the performance of interconnects (wires) that connect transistors decreases. Today, wires are dominating the performance, functionality, and power consumption of ICs.

The 3D stacking of chips or semiconductor devices is one way to address the wire problems. The transistors in ICs can now be placed closer together by arranging them in 3D instead of 2D (as it was in the 1990s). This allows for a reduction in wire length and a low delay.

There are many ways to build 3D-stacked integrated circuits and chips, including:

Toshiba demonstrated techniques for constructing 3D memories in land marks papers at VLSI 2007 & IEDM 2007. They called it-BiCS. Many memory vendors followed this work with variations and alternative designs, mostly for non-volatile memory applications like now being called 3D-NAND. These memory vendors have the important manufacturing advantage of only needing one lithography step to pattern multiple layers. These 3D Memory schemes use a lot of polysilicon as the active memory channel. This causes higher cell-to-cell performance variations and lower drive than cells with monocrystalline channels. At least one U.S. Patent. Nos. Nos. We present multiple techniques and structures for constructing 3D memory with monocrystalline channels made by alternate methods to ion-cut and subsequent layer transfers. This structure allows for multiple layers to be processed in one lithography step, which has many benefits. It also provides lower construction costs.

“In addition, all contents of U.S. Patent. Nos. Nos.

“The invention could be directed at multilayer or three-dimensional integrated circuit (3D IC), devices and fabrication methods.”

“In one embodiment, a 3D device is described, which comprises a first-level comprising logic circuits, a second level comprising multiple volatile memory cells and a third layer comprising a plurality non-volatile memories cells. The first level is bonded with the second level.

“A third aspect of the invention is a 3D device. It comprises a first-level comprising logic circuits, a second level comprising multiple dynamic memory cell arrays, and a final level comprising non-volatile storage cells. The device also includes refresh circuits for refreshing said dynamic memory cell arrays.

“A third aspect of the invention is a 3D device. It comprises a first-level comprising logic circuits, a second level comprising high speed memory cells and a third layer comprising high density memory cell. The first level is bonded with the second level and said device includes control circuits that store more than one bit per high density memory cell.

“An embodiment of the invention or combinations thereof are now described using the drawings figures. Normal skill in the art will recognize that the descriptions and figures do not limit the invention. In general, the figures are not drawn at scale to facilitate clarity. These skilled people will also see that there are many other embodiments possible using the inventive principles described herein.

“Some drawings may show process flows for building devices. A sequence of steps to build a device may include many structures, numerals, and labels. These may be shared between several steps. Some labels, numerals, and structures that were used in a particular step’s figure might have been described in previous steps’ figures.

“Memory architectures consist of at least two types: NAND and NOR. NAND architecture offers higher density because the transistors that form the memory cells are connected in serial fashion with an external connection at both the beginning and the end of each cell string. This is illustrated in at most U.S. Pat. No. 8,114,757, FIGS. 37A-37G. NOR architectures can be less dense, but offer faster access. They could also work when the NAND architecture is not available. Individual NOR memory cells and its source and drain can both be accessed. No. 8,114,757, FIGS. 30A-30M.”

The memory cell could be built with either conventional N or P type transistors, where channel doping could be of the opposite type to the source drain doping. Or the memory cell could use a junction-less transistor structure where the gate could completely deplete the channel in the off-state. The junction-less transistor may be attractive for certain architectures because it requires fewer processing steps or offers other advantages, such as a low leakage off state.

“Some 3D Memory architectures use a horizontal memory transistor for example as shown in at least U.S. Patent. No. No. 8,114,757; at most FIGS. 37A-37G, and FIGS. 30A-30M. Other types of memory transistors may be used, such as the vertical memory transistors in the Toshiba BiCS architecture, as illustrated in at most U.S. Pat. No. 7,852,675.”

Multiple methods for building 3D memory structures using horizontal transistors with junction-less transistors to form a NAND architecture and for general horizontal NAND or NOR architectures can be found in U.S. Pat. No. No. 8.114,757 in at most FIG. 33 and FIG. 37. This article will discuss multiple methods to create a multilayer silicon-oxide start structure that is equivalent to at least FIGS. 33D and 37D (of U.S. Patent. No. No. 8,114,757) without the use of an ion-cut Layer Transfer.”

“The starting structure could look similar to FIG. 41A of U.S. patent Ser. No. No. 1A. 1A. A base donor substrate 110 can be used to create a dual porous layer for future cutting layer 113. An epitaxial process could be used to produce a thick, crystalline layer 120. Future cut layer 113 could include two layers of porous silicon. An upper layer of porous silica may have microscopic pores with a diameter of just a few nanometers. Below this layer is formed a lower layer porous silicon whose pores may be several (or more!) times larger (similar to FIG. 23 of U.S. patent application Ser. No. No. 14/642,724), for the future?cut? “The epitaxial formation a relatively thick crystal layer 120 could involve successively altering dopants to support the next steps.”

“The thick crystalline layer 120 can then be transformed by anodizing to form a multilayer with alternating low porosity and high porosity, as shown in FIG. 1B, which is identical to FIG. 41B of Ser. No. 14/642,724. As described below, the alternating-porosity-multilayer can later be transformed into an alternating multilayer monocrystalline-Si over insulating SiO2. FIG. FIG. 1B shows a thick, crystalline layer 120 that has been through porous formation which creates multilayer structure 122. Multilayer structure 122 can include layers 144, layer 142, layer 140, layer 140 and layer 138. Layer 138 may also be included. Layer 136, layer 135, layer 134, and layer 132. Multilayer structure 122 could also include base donor wafer substrate 110 and porous cut layer 113, which can be used to transfer the multilayer structure fabricated over the target wafer. This may allow for the prefabrication of memory peripherals circuits on the target wafer. Multilayer structure 122 could also not include porous layer 113 if the transfer to a target Wafer is not planned. Layer 144 may be the remaining layer 120 after multi-layer processing. Alternating layers can have different porosity levels. Layers 132-136-140 could have porosity less than 30% or 40%, while layers 138, 138, and 142 could have porosity less than 50% or more than 60%. Or layers 132?136?140 could have porosity less than 55%, while layers 134?136?140 could be less than 55%. Layers 132?136, 140 could have porosity less than 55%, while layers 134?138, 142, 142 may contain porosity greater than 65% or another level depending on the process or engineering choice. Each layer could have a different porosity depending on its thickness or the number of sublayers.

The number of alternating layers in multilayer structure 122 could be increased to match the number of layers required for 3D memory. You could modulate the porosity by either (1) changing the anodizing current or (2) changing the lighting of the silicon structure during the anodizing process or (3) first switching the doping while layer 120 is being grown by epitaxial process or (4) etching and oxidizing multilayers made of SixGe1x/Si. Layer 144 could refer to the remaining portion of layer 120 that is not processed by the modulated porosity process. Here are a few examples of the above-mentioned method for forming a multilayer of c-Si/SiO2 from an alternated porous multilayer:

“For example, U.S. Pat. No. No. 7,772,096, which is incorporated herein by reference, teaches how to form a multilayer structure following (3) above, beginning with alternate doping and continuing through these steps:

“The above processing could result in the first desired multilayer structuring 122 or second desired multilayer structuring 124 for 3D memories.”

“In an embodiment (2), the epitaxial layers 120 could contain alternating n- and n+-doped layers. Light may aid in the porous formation of the layers n-doped. This will allow the anodizing process, as described by S. Frohnhoff and others, to work effectively. Thin Solid Films, U.S. Patent Applications Ser. No. 10/674,648, Ser. No. 11/038,500, Ser. No. No. No. No. 7,772,096, all of which are incorporated herein as reference. The structure can be anodized, then oxidized, and finally annealed according to steps iii-iv.

“In an embodiment (1), A method to create alternating layers of coarse porous layers is to alternate the anodizing current. This is similar to the description in?Porous silicon multilayers: A photonic gap analysis? by J. E. Lugo et al J. Appl. Phys. 91, 4966 (2002), U.S. Pat. No. 7,560,018, U.S. patent application Ser. No. No. L. Moretti, el 26 Jun. 2006/Vol. 14, No. 13, No. The structure can be anodized, then oxidized, and finally annealed according to steps iii-iv.

“The anodizing step can be performed as a single wafer or in a batch mode, as illustrated by U.S. Pat. No. No. 8.906,218, incorporated by reference and similar patents to Solexel.”

“In another embodiment, the multilayer structure may be formed by alternating n and p types. U.S. Pat. illustrates such a process. No. No. 8,470,689 in? ?Silicon millefeuille? : A silicon wafer can be transformed into multiple thin crystalline films by one step. by D. Hernandez et al., Applied Physics Letters 102, 172102 (2013); incorporated herein by reference. These methods take advantage of the fact that n-type silicon will not become porous without light, while p-type silicon would only require current to anodize. These methods could first be used to create the multilayer pattern shown in FIG. 31E or FIG. 37E of U.S. Patent. No. No. Next, the step of oxygen iii. This could be used for converting the porous layer into an isolation layer. The annealing step IV. You can make the step shorter or skip it, as the n layers may be lightly or completely etched.

“Another option is to form multilayers silicon over Si1xGex, as illustrated in?New Class of Si-based Superlattices: Alternating Layers of Crystalline Si and Porous Amorphous Si1xGex Alloys? by R. W. Fathauer et al., Appl. Phys. Lett. Lett. This multilayer structure has a high degree of selectivity when it comes to etching Si1xGex layers above Si layers. This can be followed by oxidation, such as step iii. Anneal IV. could be used to provide multiple layers of silicon over oxide. A paper entitled “Novel Three Dimensional (3D), NAND Flash Memory Array having Tied Bit-line (TiGer),”? IEICE Transactions on Electronics. It was published May 2012 and is incorporated by reference. It describes the use of multilayers silicon over Si1xGex to form a 3D NAND device. Although 3D RAM and 3D ReRAM are the most common 3D memories, the multilayer structure described herein is useful for 3D NAND type of memory. This paper was also used in process flow that was included in U.S. Pat. No. No. 8,581,349 in relation to FIG. 37A-37G are incorporated herein as a reference.”

The Bosch process is an alternative to modulated-porosity for forming cSi/SiO2 multilayers. A paper entitled Fabrication and Characterization Vertically Stacked Gate All-Around Si nanowire FET Arrays? by Davide Sacchetto et al. IEEE SDDR09, which is incorporated by reference, describes a technique for deep hole etch that has been used to create structures of crystalline lines, one on top of another, with oxide all around. Similar techniques could also be used to create the base structure of 3D memory.

“Another alternative to forming multilayer c-Si/SiO2 structures is direct epitaxy, special oxide, or silicon again. Special oxide is a rare-earth metal that, if properly deposited, would preserve the crystal structure of silicon and allow for crystalline silicon on top. This information is included in U.S. Patent Application publication US 2014/0291752 (incorporated herein by reference).

“An interesting feature of multilayer structures that are epitaxial-based, rather than layer transfer, is that most structures would look like one monolithic crystal. The crystal repeating element could be a silicon or other molecules and aligns well across layers. In layer transfer, there would be no molecular level alignment. In an epitaxial multilayer process, the molecules that form the multilayer structure are aligned at a better than 0.01 degree. However, in layer transfer base multilayer structures between layers, the molecules lines would most likely have a misalignment of more than 0.1 degrees. In an epitaxial multilayer formation, the distance between the molecules that form the multilayer structure are less than half an atomic or molecular distance.

“Using oxidized porous silicon to isolate the silicon layers of the 3D memory structure has the advantage of being able to selectively and easily etch portions of these porous layers. This allows the gate formation to have a greater coverage of the transistor channel, which will allow for increased control over the memory transistor. For example, a gate all around or a gate most? Gate all around transistor structure. Similar to the multilayer structures, the area under and on top of the channel could also be etched. This would allow for a greater coverage of the channel in the oxide and gate formation process. This could create a gate configuration all around the channel that allows for better control.

“Base wafers and substrates, acceptor wafers and substrates, as well as target wafers substrates, may all be composed of a crystalline material. This could include mono-crystalline silicon, germanium, or an engineered substrate/wafer, such an SOI (Silicon on Insulator), wafer, or GeOI(Germanium on Insulator). Similar to donor wafers, herein, donor wafers may also be substantially composed of a crystal material. They may contain mono-crystalline silicon, germanium, or an engineered substrate/wafer, such as an SOI wafer or GeOI substrate depending on the design and flow options.

The described memory structure could be described as a flow that forms a type 3D memory structure. These flows can be compared to Lego parts that could be combined in many different ways to create other variations. This could lead to many types of devices. These variations will be shown, but there are too many variations for me to list them all. These elements of architecture and process can be used by artisans to create other variations using the information provided.

“More memory structures can be made by starting with a multilayer of monocrystal layers, as shown in FIG. 1B. 1B. The multilayer structure can be prepared or partially ready by etching vertical holes or trench shapes. This allows for the completion of multilayer structure, which may include selectively etching the sacrificial layer in-between.

U.S. Patent. No. No. 8.114,757, incorporated by reference herein as related to at most FIGS. 30A-30M, FIGS. 31A-31K. This is another alternative to forming a 3D RAM volatile memory.

Multi-layers of 2D memories may be called “3D Memory”. These memory cells are placed in a matrix with rows or columns. Memory control lines, such as source-lines and bit-lines, are used to control these memory cells. This allows one to select the memory cell to read or write from by choosing a specific bit line and a specific word-line. Selecting a memory cell in a 3D matrix with three dimensions requires that the layer be selected. Additional memory control lines, such as select-lines, may also be used to do this. Some of the select lines, as shown in FIGS. 8F and 85. Others lines can be formed by epitaxial growth or deposited. These memory control lines can be made up of semiconductor materials like silicon, or conductive metal layers like tungsten aluminum and copper. FIGS. 3, 4 and 5 of the incorporated application U.S. 62/215,112.”

“Another option that doesn’t require any changes to the device structure is to use what might be called “self refresh”. A refresh cycle is a process in which each cell is read and rewritten separately. Self refresh is a process that allows each cell to be read and re-written individually. Many or all of the cells can be refreshed by driving a certain current through them. The cell holding zero? The cell holding ‘zero? will retain its zero state, while the one holding?one? will remain at?zero? They will be recharged to replenish their floating body charge lost due to leakage. Takashi Ohsawa and colleagues described this technique in a paper. al. In paper titled: ‘Autonomous Refreshing of Floating Body Cells (FBC). Published in IEDM 2008. Follow up paper:?Autonomous Reveal of Floating Body Cell (FBC)? Published by IEEE TRANSACTIONS ELECTRON DEVICES VOL. 56, NO. 56, NO. Nos. Nos. 8,194,487, and 8,446,794, are all incorporated herein by reference.”

“Another type is resistive-memory. (?ReRAM?) This is a non-volatile type of memory. U.S. Pat. No. No. 9,117,749, which is incorporated by reference. ReRAM is a memory function that has the ability to change the resistivity. This could be done by driving current through the ReRAM variable resistance medium. It could also be sensed by measuring voltage or current through that medium. ReRAM could be made from many materials, including oxides that have additional materials that can be added to the oxide to increase its resistivity. U.S. Pat. No. No. 8.390,326 is incorporated by reference and shows the use of silicon dioxide for such purposes. ReRAM structures that permit only one-time programming (?OTP?) are a subclass of the ReRAM. These mediums are similar to those described in U.S. Pat. No. No. 8.330,189 is incorporated herein as a reference.”

Ahmad Z. Badwan and co. described a T-RAM cell in a paper. al. Titled?SOI Field Effect Diode DRAM cell: Design and Operation? Published in IEEE Electron Device Letters Vol. 34, No. 8 August 2013, incorporated by reference. This T-RAM structure and the process to create them could be modified to make FED (Field Effect Diode) structures and to make a 3D-FED RAM.

U.S. Patent. No. No. 8.114,757, incorporated by reference herein as related to at most FIGS. 30A-30M, FIGS. 31A-31K. This is another alternative to forming a 3D RAM volatile memory.

Multi-layers of 2D memories may be called “3D Memory”. These memory cells are placed in a matrix with rows or columns. Memory control lines, such as source-lines and bit-lines, are used to control these memory cells. This allows one to select the memory cell to read or write from by choosing a specific bit line and a specific word-line. Selecting a memory cell in a 3D matrix with three dimensions requires that the layer be selected. Additional memory control lines, such as select-lines, may also be used to do this. Some of the select lines, as shown in FIGS. 8F and 85. Others lines can be formed by epitaxial growth or deposited. These memory control lines may contain semiconductor materials like silicon, or conductive metal layers like tungsten aluminum and copper.

“FIG. 3A shows a multilayer structure that starts with silicon 304 or n-type silicon 302, and an isolation layer or sacrificial layers in-between 306 which is formed using many of the methods described herein. For the next etch step, a hard mask 308 like silicon nitride can be used to pattern on top. These 3D memories flows have an important advantage, as shown in the following: only one lithography step is required to affect multiple layers. This concept will be used in many memory flows.

“FIG. “FIG.

“FIG. 3C shows the structure 311 after SiO2 has been deposited and 314 holes have been etched for the next step of gate stack.

“FIG. The structure of the gate stack 322 after it has been formed in 3D. The gate stack could include agate dentric and agate electrode material. This could be made by CVD/ALD of first a gateoxide and then a gate material. It could also be made from metal or in-situ doped with polysilicon. Radical oxidation is another method that can be used to produce a high-quality thermal oxide. TEL SPA (slot-plan antenna) is a tool/machine that generates oxygen radicals and uses them to form thin thermal dioxides. These oxides can be formed at temperatures below 400 degrees C. It may be necessary to include a non-directional, isotropic etch step in order to create the next gate.

“FIG. 3E shows the structure 321 after stripping the dielectric 312, followed by diffusion doping to form both the drain regions 326 and the source 324 regions. The source regions 324 would connect to the source line (??SL?). The source regions 324 would be connected to the source line (?SL?). Depending on the arrangement of the array, the SL or BL can also be interchangeable. Diffusion doping converts all exposed silicon areas not covered by the gates 322 from p to n+ or n to p+ types. The transistors will be created in the small pin structure 325. The common strips 327 will serve as simple conductors acting as bit-lines and source-lines for memories that could form by the pins transistors 325.

“FIG. 3F shows the structure 331 and the extension of the bitlines 334 that could be used to create a staircase per layer access. A select gate 332 can be used to select a memory branch.

“FIG. 3G shows the structure 331 after the formation of the stair-case 336 for the bit line extension 334, and after the formation of the vertical connections to bit-lines 337 and transistor sources 338.”

“FIG. 3H shows the structure after adding the grid. This illustration can be used to structure bit-lines 356, select lines 358, sourcelines 352 or word-lines 350. The corner direction 359 illustrates the direction x,y,z. These connectivity structures allow us to select a cell so that we can choose the?x? gate lines 358. Select the?x? location. branch, the word-lines 354 choose the?y? Locate the gate in?y by choosing the word-lines 354 direction. The bit-lines 356 choose the?z? Select the drain in??z? direction. Optional select-gate lines 358 permit selection of the bank transistors along?x? direction.”

“FIG. 3I shows the structure after adding the grid with connections using an alternative structure of bit-lines and word-lines. The common gate material runs along the multiple pins. This would act as a simple conductor and word-lines.

“FIG. “FIG. Only the areas that are designated for silicification 362 are exposed, while all others are protected with photoresist and isolation oxide. Next, a metal, such as Ni Ti, Co or another known in the art material is applied to the bit lines 362. Thermal reaction can then be achieved using Rapid Thermal Anneal or laser anneal. The unreacted metal can then be etched.

“FIG. 3K is a 3D memory with a three column structure. The vertical line 338 in FIG. connects the transistors source that form the memory cell. 3G connects with the transistors source sidewall. FIG. 3K. This vertical connection could also be formed by selective epitaxy, an alternative to deposition.

“FIG. 3L shows the structure with protective covering of oxide or another protective material 366, and trench opening the sides of the memory transistors source 368. This could be a step to remove a portion of the vertical isolation between sources of stack transistors by opening the trenches 366.

“FIG. 3M shows the structure after epitaxial growth to form a vertical column connecting all sources in a stack. These columns could be silicided to improve their connectivity.

“FIG. 3N shows the structure after adding contacts 372 to the top.

FIGS. 3A-3N were created for easy understanding and drawing. People skilled in the art will understand that memory bit density can be increased using techniques used in memory design. Mirroring transistors along bit lines that are shared by right and left sides of the transistors, and mirroring across the source side to share the vertical source lines. U.S. Pat. illustrates such a structure. No. No. 8.114,757 as related to FIGS. 30A-30M and FIGS. 31A-31K.”

“FIG. 3O shows another alternative. The vertical line connecting the source side to the stack transistors 376 is shared, but the horizontal silicon bit-lines first and second bit?line 374 and 375 are not shared. The advantage to not sharing bit-lines 1 bit-line 374 or 2 bit-line 375 is that you can add silicidation, as described in FIG. 3J.”

“FIG. 3P is an alternative. The horizontal bit lines 384 of the stack transistors are shared, but not the vertical line connecting to the source side of 385 and 386 of the stack transistors are shared.”

“FIG. 4A shows a charge storage (may include a floating-body, charge trap, or other types). Memory cell of the type used for 3D RAM, as shown in FIG. 3A-3P is an enhanced version of the type used for 3D RAM, as illustrated in FIG. The memory cell could have a n-type drain 402, p-type channel 404, and a n-type source 406. In place of the single gate layer process described above, successive steps of ALD (Atomic Layer Deposition), or another type of deposition, could be used to form the tunneling oxide, charge storage layer, 414, 416, and gate 408. This memory is also known as universal memory. Each memory cell can function as both high speed volatile RAM or low power non-volatile floating gates or charge trap memories. Combining high speed RAM and low-power non-volatile back-up might be attractive for some applications. U.S. Pat. also presents a dual-use channel. No. 7,158,410 and papers by J. W. Han. titled “A Unified RAM (URAM), Cell for Multi-Functioning Capacitorless NRAM and DRAM?” Published by IEDM 2007, Dong-Il Moon et al. The title of the paper is ‘Evolution of Unified RAM: 1T DRAM and BE-SONOS Built On a Highly Scaled Vertical channel? Published at IEEE TRANSACTIONS ELECTRON DEVICES VOL. 61, NO. 1, JANUARY 2014. All of the above are incorporated herein as reference.”

“FIG. 4B shows enhancements to the FIG. 4A to the 3D memory as shown in FIG. 3A-3P.”

“FIG. 4C shows enhancements to the FIG. FIG. 4A is the 3D memory illustration. 14A-14H U.S. Patent Application No. 62/221/618, incorporated herein as a reference.”

“In U.S. Pat. No. No. 8.902,663, incorporated by reference. A select transistor is shown at the top layer of a 3D column memory cell column, as described in FIG. 8 and the associated description there. This per column select transistor could prove to be useful for many of these memory structures. This top layer select transistor can be combined with the transistors that form the memory cell beneath it by using the same lithography process. Thus, the top select transistor is at least partially aligned with the memory cells below. These select transistors can provide additional control and can be used as a buffer for the memory cells, which could improve memory access speed and aid in read and write operations. The following describes the steps involved in adding select transistors to the 3D TRAM structure. A semiconductor memory artisan would easily be able to apply this concept to any of the memory structures presented herein.

“FIG. 5A illustrates prior art 2D memory device. Memory control circuits 504 surround the memory cells 2D matrix 502 and include decoders, sense amplifiers and interfaces to external devices. Memory peripherals are the circuits 504. The memory control lines 506 run across the memory array rows and columns, miming to the peripherals circuits.

“FIG. “FIG.5” 5B shows a side view of a cross-section of a prior art 3D memory device. 3D memory, also known as 3D NAND, has recently been introduced to the market. The memory cell 3D matrix512 of such 3D-NAND is still surrounded and controlled by 514 memory control circuits. These include decoders, sense amps, interfaces with external devices and amplifiers. These memory peripheral circuits are processed in a similar manner to the 2D memory circuits built on silicon wafer substrate. These 3D memories have control lines 516 that run through the rows and columns of the memory matrix. Some control lines are built on top of 3D matrix while others are going through the bulk of the matrix. However, at the edges they are connected to 2D peripheral circuits.

“FIG. “FIG. The 3D memory matrix 522 includes columns and rows with the control circuits 524. These could still be called peripherals, but could be built on top of the matrix. In this embodiment, control lines 526 are placed underneath the peripheral circuits and in-between the memory matrix 522 and 524.

“FIG. 5D shows a side-view crosssection of alternative 3D memories made using the techniques herein. The control lines and control circuits are located underneath the memory cell matrix.

“This new type 3D memory could be constructed to gain significant advantage over prior art by using the 3D architecture illustrated in at most FIGS. 5C and 5D to divide the control lines 526 into smaller pieces. Each chunk will have its control circuits repeated. A shorter control line could reduce memory access read, write, refresh and speed up memory access time. If the stair-case is used for layer access too often, it could affect device cost. To save overhead space, proper architecture and overall memory control strategy could utilize long per-layer control lines (not illustrated). Therefore, it is important to design the memory architecture to allow for long control lines to memory within the same layers for as long as possible. Keeping the vertical control lines short and the per-layer control lines long could provide the advantages of low power and fast access for most of the time.

“As discussed with FIG. 4A, FIG. 4A, FIG. 4B, and FIG. These are non-volatile cells that use floating gate or charge trap technology. Other non-volatile memory technology options, such as M-RAM and Phase-Change or Re-RAM could also be used. Splitting the gates on one side of the memory channel could be used to control the volatile function, while the other side could be used for non-volatile functions. Splitting the gate could also be used to increase non-volatile memory density for cells with enough channel to support 2-bit per cell techniques.

“In most cases, volatile operation could interfere avec the non-volatile operations of the memory cells. It is best to not use them together and to have the unused section reset electrically to minimize interference with the used.

There are many ways that such enhanced memory can be used. These include powering down to save volatile information in the non-volatile section, and reducing sleep power by moving volatile information into non-volatile. The 3D structures shown in this figure have control circuits at the top and/or bottom for some of these uses modes. FIG. 5B and FIG. 5B and FIG. These modes could reduce the time and power needed to transfer data from volatile into non volatile portions by an order of magnitude.

“FIG. “FIG. The interface to external devices is controlled by the side memory control circuits 601. They can be used for both instruction and data input and out. These circuits 601 may include per-layer decoders. They also control the internal memory blocks. This could reduce the stair-case overhead. Each block 602 is a sub-memory with its own top peripherals circuits that control most of the control lines. This design allows data to be moved from one section to another in parallel. These operations could be synchronized by the side memory control circuits 601 so that they can be performed one layer at a.m.

“FIG. 6B shows the block diagram for a peripherals circuit in a block 602. This block diagram 604 could show you the block diagram of a unit block control circuit.

“Central controller 630 commands and controls these operations for sleep mode, recovery mode, etc.”

“In-Out interface controller to interface data and with device controller 601”

“Sense Amplifiers620 are used to sense data from a memory cell according the mode of operation, and to convert side-memory control circuits 601 into a digital bit that could be temporarily stored within the unit memory cash 634.”

“Signal generators 618 are used to generate the voltages and currents required for proper read/write of memory cells. These circuitry, including charge pumps, can be shared among all units and placed in side memory control circuits 601.

Blocks 612-614, 616 and 617 are for various control lines like bit-lines or word-lines. The 616 layer decoders could be removed from unit 604 and placed in the general per-layer circuits at the side memory control circuits 601.

This memory architecture has the added advantage of allowing you to access large blocks of data simultaneously, as many blocks 602 can be accessed at once. To maximize array efficiency, only one per-layer staircase should be used. This would limit parallel action to one layer. This could be controlled by proper system data structure.

“This 3D Memory could also include redundancy circuitry that allows for repair and replacement of memory bits. FIG. FIG. 5D could be used to access substantially all memory control lines on both sides?top and bottom, and to duplicate the device control circuit 524 at bottom. This redundancy scheme could be reduced to the level of memory block control units 602. If one unit block control circuit is defective, it can be replaced with a compatible one at the opposite end. As an alternative, each unit block control circuitry can be constructed with two stratums. One is a backup for the other.

“The memory control redundancy could apply to any of these 3D memories.”

FIGS. 7-13 show another embodiment of monolithic, 3D memory according the present invention. FIGS. 7-13 are outlined below. Mono-crystalline transistors are used. The channels of mono-crystalline transistors run vertically so that current flows vertically across the device’s layers, rather than horizontally. This structure is low-cost because it uses the same lithography, deposition, and etch techniques as multiple layers to form self-aligned, vertically oriented transistors.

“FIG. 7A shows the starting material structure of these vertically oriented 3D memories. It contains interchanging layers of designated source/drain material 702 and designated channel material 704. These layers can be processed epitaxially using in-situ alternating P/P+ to N/N+ doping or between SiGe and alternating silicon layers, etc. You may consider using a high-etch selectivity process to etch adjacent layers faster than the (S/D), layers 702. This will allow for a more efficient composition of these layers. These layers can be as thin as a few nm to hundreds of millimeters thick. Dopant diffusion suppression may also be achieved by low-temperature epitaxial processes such the AMAT 450-500 degrees C. epi process. Interlayer diffusion barriers can also be used, for example, a thin, single, or double atomic layer of an anti-diffusion suppressor like carbon.

“For instance, the composition of the S/D layer 702 could be N+ silica while the channel layer 704 could contain P type silicon. The selective etch process would use anodic etching described in U.S. Pat. No. No. 8,470,689 as described herein.

“An alternative to using P++ silicon is to use S/D layers 702 & N silicon channel layers 704; the later selective etch would be performed with the NH4OH solution, as suggested by Golod et al.”

“Yet another option is to use N+ silica for (S/D), layers 702 and 704, and P type SiGe channel layers 704, and the later selectiveetch would utilize the process described by Se Hwan Park and colleagues in a piper entitled?Novel (3D) NAND flash memory array having tied bit-line and ground select transistor (TiGer). Published in TECHNICAL RELEASE OF IEICE 711 (APWF_PSH), a paper written by F L W. Fathauer et all titled ‘New class of Si-based Superlattices: Alternating Layers of Crystal Si and Porous Amorphous Si, ?, Ge, Alloys? Published by Appl. Phys. Lett. Lett. Published at IEEE TRANSACTIONS ELECTRON DEVICES VOL. 58, NO. 4, APRIL 2011, and U.S. Pat. No. No. 8,501,609 are all incorporated herein as reference.”

“For simplicity, we will outline the flow of a vertical channel 3D structure memory including S/D layers 702 and N+ silicon as well as channel layers 704. Any person skilled in the arts would be able modify the flow to accommodate other embodiments.

“On top the multilayer of alternating 702/704 is deposited a hard mask material 706.

“FIG. 7B shows how etching the structure to create multilayer ridges 709, and valleys 708 between them resulted in repeating-ridges structure 707. The valleys and ridges can be as wide as 10 nm, or lower than that to hundreds of nm. A good choice at the moment is 50 nm. Consider the thickness of layers 702/704, type of memory built, and other factors when determining the width of the valleys and ridges. A similar width and thickness might be possible.”

“FIG. 7C shows the structure after selective isotropic etching of channel layers 704 to form horizontal notches 719, while leaving the S/D layers 710 untouched. You can use a selective plasma etch. You can increase the selectivity by first creating pores in the desired areas of the channel layers using selective anodization. This would allow plasma etch to be extremely selective. Warm KOH can also be used to selectively etch the crystallographic planes 100>.

“FIG. 7D shows the structure after depositing a stack tunneling oxide/charge trap/control oxide layers 712 such as oxide/nitride/oxide or gate conductive material 714. This step can be performed by Atomic Layer Deposition or other processes for fabricating semiconductor devices. To remove substantial amounts of gate material from the sides of the S/D 713 layers, a directional anisotropic step could be used. Stringers can also be removed by a slight touch-up isotropicetch.

“FIG. 7E shows the structure after filling in the trenches 708 (FIG. 7B is filled with insulating material 716. An etch step then forms vertical gaps 710 along the ridges 709 of FIG. 7B to create vertical strings 722 from alternating N+/P materials. Two steps could be used to etch the stack of multilayers of alternating 702/704 to form vertical strings 722. Anisotropic etch first the stack of multilayers of alternating 702/704 in order to form the vertical individual string 722. Then, isotropic selectively etch to remove source/drain 702 between the gate stack 712. While leaving the horizontal going gates and oxide lines. To serve as a common ground, the etching can be stopped prior to the lowest N+ layer. You may also use conductive etch-stop layers.

“FIG. 7F shows a vertical cross-sectional view of FIG. 7E. 7E. The common ground line could be the remaining bottom material 738. Ground select gate could be the lower gate line 740. The string drain area would be located at the top of the strings 732 and could be connected to the bit-lines later. This structure creates a matrix of vertically-oriented non-volatile NAND memories cells. Horizontal control gates 742 are the memory word lines that control current through the vertical channels. They may also form vertical NAND strings.

“FIG. 7G shows a vertical cross-section of one vertical NAND string 736 perpendicularly to the direction of the metal-gate-word-line.

“FIG. 7H shows the 3D NAND structure after adding the grid memory control lines: word, bit, string, select-lines 767 and ground select-lines 751.

“In this 3D structure of memory, as well as in all other memory structures, the horizontal per-layer line through the matrix could limit the power performance of a device in terms of how long it can be made. To save silicon real-estate, and to reduce costs per bit, the lines required for the interconnect structure of the stair-cases must be longer. This stair-case could be placed on either side of the line, which can help to reduce cell to cell variation and improve power and delay. Splitting the device into multiple blocks can improve real estate efficiency by sharing each staircase between the right and left sides of each block.

“FIG. 8A shows a structure that can be used to form a NOR 3D memory. It begins with FIG. 20B of the U.S. Patent Application 62/221 618. To form the charge storage stack 802, first elongated strips are formed using etching and masking techniques. These strips are coated with a dielectric multilayer tunneling-oxide, charge-trap, and control gate oxide layers. A gate 804 material, such as tungsten (W), or polysilicon, is deposited on top. The charge storage stack 802 or gate overcoat 804 are patterned using masking and etching techniques in order to form second elongated stripes perpendicularly to said first elongated strip. ALD techniques could be used for the deposition step.

Summary for “3D semiconductor device, structure”

“1. “1.

“This application relates generally to Integrated Circuit (IC), devices and fabrication techniques, but more specifically to multilayer (3D-Memory), devices and fabrication methodologies.”

“2. “2.

“In the last 40 years there has been a significant increase in the functionality and performance of Integrated Circuits. This is largely due to the phenomenon known as “scaling?” This refers to the fact that component sizes, such as lateral or vertical dimensions, within ICs have been decreased (?scaled?) Each successive generation of technology. Complementary Metal Oxide Semiconductor ICs have two main types of components: wires and transistors. Typically, transistor performance and density improve with?scaling”. This has led to the above-mentioned improvements in IC functionality and performance. With?scaling?, however, the performance of interconnects (wires) that connect transistors decreases. Today, wires are dominating the performance, functionality, and power consumption of ICs.

The 3D stacking of chips or semiconductor devices is one way to address the wire problems. The transistors in ICs can now be placed closer together by arranging them in 3D instead of 2D (as it was in the 1990s). This allows for a reduction in wire length and a low delay.

There are many ways to build 3D-stacked integrated circuits and chips, including:

Toshiba demonstrated techniques for constructing 3D memories in land marks papers at VLSI 2007 & IEDM 2007. They called it-BiCS. Many memory vendors followed this work with variations and alternative designs, mostly for non-volatile memory applications like now being called 3D-NAND. These memory vendors have the important manufacturing advantage of only needing one lithography step to pattern multiple layers. These 3D Memory schemes use a lot of polysilicon as the active memory channel. This causes higher cell-to-cell performance variations and lower drive than cells with monocrystalline channels. At least one U.S. Patent. Nos. Nos. We present multiple techniques and structures for constructing 3D memory with monocrystalline channels made by alternate methods to ion-cut and subsequent layer transfers. This structure allows for multiple layers to be processed in one lithography step, which has many benefits. It also provides lower construction costs.

“In addition, all contents of U.S. Patent. Nos. Nos.

“The invention could be directed at multilayer or three-dimensional integrated circuit (3D IC), devices and fabrication methods.”

“In one embodiment, a 3D device is described, which comprises a first-level comprising logic circuits, a second level comprising multiple volatile memory cells and a third layer comprising a plurality non-volatile memories cells. The first level is bonded with the second level.

“A third aspect of the invention is a 3D device. It comprises a first-level comprising logic circuits, a second level comprising multiple dynamic memory cell arrays, and a final level comprising non-volatile storage cells. The device also includes refresh circuits for refreshing said dynamic memory cell arrays.

“A third aspect of the invention is a 3D device. It comprises a first-level comprising logic circuits, a second level comprising high speed memory cells and a third layer comprising high density memory cell. The first level is bonded with the second level and said device includes control circuits that store more than one bit per high density memory cell.

“An embodiment of the invention or combinations thereof are now described using the drawings figures. Normal skill in the art will recognize that the descriptions and figures do not limit the invention. In general, the figures are not drawn at scale to facilitate clarity. These skilled people will also see that there are many other embodiments possible using the inventive principles described herein.

“Some drawings may show process flows for building devices. A sequence of steps to build a device may include many structures, numerals, and labels. These may be shared between several steps. Some labels, numerals, and structures that were used in a particular step’s figure might have been described in previous steps’ figures.

“Memory architectures consist of at least two types: NAND and NOR. NAND architecture offers higher density because the transistors that form the memory cells are connected in serial fashion with an external connection at both the beginning and the end of each cell string. This is illustrated in at most U.S. Pat. No. 8,114,757, FIGS. 37A-37G. NOR architectures can be less dense, but offer faster access. They could also work when the NAND architecture is not available. Individual NOR memory cells and its source and drain can both be accessed. No. 8,114,757, FIGS. 30A-30M.”

The memory cell could be built with either conventional N or P type transistors, where channel doping could be of the opposite type to the source drain doping. Or the memory cell could use a junction-less transistor structure where the gate could completely deplete the channel in the off-state. The junction-less transistor may be attractive for certain architectures because it requires fewer processing steps or offers other advantages, such as a low leakage off state.

“Some 3D Memory architectures use a horizontal memory transistor for example as shown in at least U.S. Patent. No. No. 8,114,757; at most FIGS. 37A-37G, and FIGS. 30A-30M. Other types of memory transistors may be used, such as the vertical memory transistors in the Toshiba BiCS architecture, as illustrated in at most U.S. Pat. No. 7,852,675.”

Multiple methods for building 3D memory structures using horizontal transistors with junction-less transistors to form a NAND architecture and for general horizontal NAND or NOR architectures can be found in U.S. Pat. No. No. 8.114,757 in at most FIG. 33 and FIG. 37. This article will discuss multiple methods to create a multilayer silicon-oxide start structure that is equivalent to at least FIGS. 33D and 37D (of U.S. Patent. No. No. 8,114,757) without the use of an ion-cut Layer Transfer.”

“The starting structure could look similar to FIG. 41A of U.S. patent Ser. No. No. 1A. 1A. A base donor substrate 110 can be used to create a dual porous layer for future cutting layer 113. An epitaxial process could be used to produce a thick, crystalline layer 120. Future cut layer 113 could include two layers of porous silicon. An upper layer of porous silica may have microscopic pores with a diameter of just a few nanometers. Below this layer is formed a lower layer porous silicon whose pores may be several (or more!) times larger (similar to FIG. 23 of U.S. patent application Ser. No. No. 14/642,724), for the future?cut? “The epitaxial formation a relatively thick crystal layer 120 could involve successively altering dopants to support the next steps.”

“The thick crystalline layer 120 can then be transformed by anodizing to form a multilayer with alternating low porosity and high porosity, as shown in FIG. 1B, which is identical to FIG. 41B of Ser. No. 14/642,724. As described below, the alternating-porosity-multilayer can later be transformed into an alternating multilayer monocrystalline-Si over insulating SiO2. FIG. FIG. 1B shows a thick, crystalline layer 120 that has been through porous formation which creates multilayer structure 122. Multilayer structure 122 can include layers 144, layer 142, layer 140, layer 140 and layer 138. Layer 138 may also be included. Layer 136, layer 135, layer 134, and layer 132. Multilayer structure 122 could also include base donor wafer substrate 110 and porous cut layer 113, which can be used to transfer the multilayer structure fabricated over the target wafer. This may allow for the prefabrication of memory peripherals circuits on the target wafer. Multilayer structure 122 could also not include porous layer 113 if the transfer to a target Wafer is not planned. Layer 144 may be the remaining layer 120 after multi-layer processing. Alternating layers can have different porosity levels. Layers 132-136-140 could have porosity less than 30% or 40%, while layers 138, 138, and 142 could have porosity less than 50% or more than 60%. Or layers 132?136?140 could have porosity less than 55%, while layers 134?136?140 could be less than 55%. Layers 132?136, 140 could have porosity less than 55%, while layers 134?138, 142, 142 may contain porosity greater than 65% or another level depending on the process or engineering choice. Each layer could have a different porosity depending on its thickness or the number of sublayers.

The number of alternating layers in multilayer structure 122 could be increased to match the number of layers required for 3D memory. You could modulate the porosity by either (1) changing the anodizing current or (2) changing the lighting of the silicon structure during the anodizing process or (3) first switching the doping while layer 120 is being grown by epitaxial process or (4) etching and oxidizing multilayers made of SixGe1x/Si. Layer 144 could refer to the remaining portion of layer 120 that is not processed by the modulated porosity process. Here are a few examples of the above-mentioned method for forming a multilayer of c-Si/SiO2 from an alternated porous multilayer:

“For example, U.S. Pat. No. No. 7,772,096, which is incorporated herein by reference, teaches how to form a multilayer structure following (3) above, beginning with alternate doping and continuing through these steps:

“The above processing could result in the first desired multilayer structuring 122 or second desired multilayer structuring 124 for 3D memories.”

“In an embodiment (2), the epitaxial layers 120 could contain alternating n- and n+-doped layers. Light may aid in the porous formation of the layers n-doped. This will allow the anodizing process, as described by S. Frohnhoff and others, to work effectively. Thin Solid Films, U.S. Patent Applications Ser. No. 10/674,648, Ser. No. 11/038,500, Ser. No. No. No. No. 7,772,096, all of which are incorporated herein as reference. The structure can be anodized, then oxidized, and finally annealed according to steps iii-iv.

“In an embodiment (1), A method to create alternating layers of coarse porous layers is to alternate the anodizing current. This is similar to the description in?Porous silicon multilayers: A photonic gap analysis? by J. E. Lugo et al J. Appl. Phys. 91, 4966 (2002), U.S. Pat. No. 7,560,018, U.S. patent application Ser. No. No. L. Moretti, el 26 Jun. 2006/Vol. 14, No. 13, No. The structure can be anodized, then oxidized, and finally annealed according to steps iii-iv.

“The anodizing step can be performed as a single wafer or in a batch mode, as illustrated by U.S. Pat. No. No. 8.906,218, incorporated by reference and similar patents to Solexel.”

“In another embodiment, the multilayer structure may be formed by alternating n and p types. U.S. Pat. illustrates such a process. No. No. 8,470,689 in? ?Silicon millefeuille? : A silicon wafer can be transformed into multiple thin crystalline films by one step. by D. Hernandez et al., Applied Physics Letters 102, 172102 (2013); incorporated herein by reference. These methods take advantage of the fact that n-type silicon will not become porous without light, while p-type silicon would only require current to anodize. These methods could first be used to create the multilayer pattern shown in FIG. 31E or FIG. 37E of U.S. Patent. No. No. Next, the step of oxygen iii. This could be used for converting the porous layer into an isolation layer. The annealing step IV. You can make the step shorter or skip it, as the n layers may be lightly or completely etched.

“Another option is to form multilayers silicon over Si1xGex, as illustrated in?New Class of Si-based Superlattices: Alternating Layers of Crystalline Si and Porous Amorphous Si1xGex Alloys? by R. W. Fathauer et al., Appl. Phys. Lett. Lett. This multilayer structure has a high degree of selectivity when it comes to etching Si1xGex layers above Si layers. This can be followed by oxidation, such as step iii. Anneal IV. could be used to provide multiple layers of silicon over oxide. A paper entitled “Novel Three Dimensional (3D), NAND Flash Memory Array having Tied Bit-line (TiGer),”? IEICE Transactions on Electronics. It was published May 2012 and is incorporated by reference. It describes the use of multilayers silicon over Si1xGex to form a 3D NAND device. Although 3D RAM and 3D ReRAM are the most common 3D memories, the multilayer structure described herein is useful for 3D NAND type of memory. This paper was also used in process flow that was included in U.S. Pat. No. No. 8,581,349 in relation to FIG. 37A-37G are incorporated herein as a reference.”

The Bosch process is an alternative to modulated-porosity for forming cSi/SiO2 multilayers. A paper entitled Fabrication and Characterization Vertically Stacked Gate All-Around Si nanowire FET Arrays? by Davide Sacchetto et al. IEEE SDDR09, which is incorporated by reference, describes a technique for deep hole etch that has been used to create structures of crystalline lines, one on top of another, with oxide all around. Similar techniques could also be used to create the base structure of 3D memory.

“Another alternative to forming multilayer c-Si/SiO2 structures is direct epitaxy, special oxide, or silicon again. Special oxide is a rare-earth metal that, if properly deposited, would preserve the crystal structure of silicon and allow for crystalline silicon on top. This information is included in U.S. Patent Application publication US 2014/0291752 (incorporated herein by reference).

“An interesting feature of multilayer structures that are epitaxial-based, rather than layer transfer, is that most structures would look like one monolithic crystal. The crystal repeating element could be a silicon or other molecules and aligns well across layers. In layer transfer, there would be no molecular level alignment. In an epitaxial multilayer process, the molecules that form the multilayer structure are aligned at a better than 0.01 degree. However, in layer transfer base multilayer structures between layers, the molecules lines would most likely have a misalignment of more than 0.1 degrees. In an epitaxial multilayer formation, the distance between the molecules that form the multilayer structure are less than half an atomic or molecular distance.

“Using oxidized porous silicon to isolate the silicon layers of the 3D memory structure has the advantage of being able to selectively and easily etch portions of these porous layers. This allows the gate formation to have a greater coverage of the transistor channel, which will allow for increased control over the memory transistor. For example, a gate all around or a gate most? Gate all around transistor structure. Similar to the multilayer structures, the area under and on top of the channel could also be etched. This would allow for a greater coverage of the channel in the oxide and gate formation process. This could create a gate configuration all around the channel that allows for better control.

“Base wafers and substrates, acceptor wafers and substrates, as well as target wafers substrates, may all be composed of a crystalline material. This could include mono-crystalline silicon, germanium, or an engineered substrate/wafer, such an SOI (Silicon on Insulator), wafer, or GeOI(Germanium on Insulator). Similar to donor wafers, herein, donor wafers may also be substantially composed of a crystal material. They may contain mono-crystalline silicon, germanium, or an engineered substrate/wafer, such as an SOI wafer or GeOI substrate depending on the design and flow options.

The described memory structure could be described as a flow that forms a type 3D memory structure. These flows can be compared to Lego parts that could be combined in many different ways to create other variations. This could lead to many types of devices. These variations will be shown, but there are too many variations for me to list them all. These elements of architecture and process can be used by artisans to create other variations using the information provided.

“More memory structures can be made by starting with a multilayer of monocrystal layers, as shown in FIG. 1B. 1B. The multilayer structure can be prepared or partially ready by etching vertical holes or trench shapes. This allows for the completion of multilayer structure, which may include selectively etching the sacrificial layer in-between.

U.S. Patent. No. No. 8.114,757, incorporated by reference herein as related to at most FIGS. 30A-30M, FIGS. 31A-31K. This is another alternative to forming a 3D RAM volatile memory.

Multi-layers of 2D memories may be called “3D Memory”. These memory cells are placed in a matrix with rows or columns. Memory control lines, such as source-lines and bit-lines, are used to control these memory cells. This allows one to select the memory cell to read or write from by choosing a specific bit line and a specific word-line. Selecting a memory cell in a 3D matrix with three dimensions requires that the layer be selected. Additional memory control lines, such as select-lines, may also be used to do this. Some of the select lines, as shown in FIGS. 8F and 85. Others lines can be formed by epitaxial growth or deposited. These memory control lines can be made up of semiconductor materials like silicon, or conductive metal layers like tungsten aluminum and copper. FIGS. 3, 4 and 5 of the incorporated application U.S. 62/215,112.”

“Another option that doesn’t require any changes to the device structure is to use what might be called “self refresh”. A refresh cycle is a process in which each cell is read and rewritten separately. Self refresh is a process that allows each cell to be read and re-written individually. Many or all of the cells can be refreshed by driving a certain current through them. The cell holding zero? The cell holding ‘zero? will retain its zero state, while the one holding?one? will remain at?zero? They will be recharged to replenish their floating body charge lost due to leakage. Takashi Ohsawa and colleagues described this technique in a paper. al. In paper titled: ‘Autonomous Refreshing of Floating Body Cells (FBC). Published in IEDM 2008. Follow up paper:?Autonomous Reveal of Floating Body Cell (FBC)? Published by IEEE TRANSACTIONS ELECTRON DEVICES VOL. 56, NO. 56, NO. Nos. Nos. 8,194,487, and 8,446,794, are all incorporated herein by reference.”

“Another type is resistive-memory. (?ReRAM?) This is a non-volatile type of memory. U.S. Pat. No. No. 9,117,749, which is incorporated by reference. ReRAM is a memory function that has the ability to change the resistivity. This could be done by driving current through the ReRAM variable resistance medium. It could also be sensed by measuring voltage or current through that medium. ReRAM could be made from many materials, including oxides that have additional materials that can be added to the oxide to increase its resistivity. U.S. Pat. No. No. 8.390,326 is incorporated by reference and shows the use of silicon dioxide for such purposes. ReRAM structures that permit only one-time programming (?OTP?) are a subclass of the ReRAM. These mediums are similar to those described in U.S. Pat. No. No. 8.330,189 is incorporated herein as a reference.”

Ahmad Z. Badwan and co. described a T-RAM cell in a paper. al. Titled?SOI Field Effect Diode DRAM cell: Design and Operation? Published in IEEE Electron Device Letters Vol. 34, No. 8 August 2013, incorporated by reference. This T-RAM structure and the process to create them could be modified to make FED (Field Effect Diode) structures and to make a 3D-FED RAM.

U.S. Patent. No. No. 8.114,757, incorporated by reference herein as related to at most FIGS. 30A-30M, FIGS. 31A-31K. This is another alternative to forming a 3D RAM volatile memory.

Multi-layers of 2D memories may be called “3D Memory”. These memory cells are placed in a matrix with rows or columns. Memory control lines, such as source-lines and bit-lines, are used to control these memory cells. This allows one to select the memory cell to read or write from by choosing a specific bit line and a specific word-line. Selecting a memory cell in a 3D matrix with three dimensions requires that the layer be selected. Additional memory control lines, such as select-lines, may also be used to do this. Some of the select lines, as shown in FIGS. 8F and 85. Others lines can be formed by epitaxial growth or deposited. These memory control lines may contain semiconductor materials like silicon, or conductive metal layers like tungsten aluminum and copper.

“FIG. 3A shows a multilayer structure that starts with silicon 304 or n-type silicon 302, and an isolation layer or sacrificial layers in-between 306 which is formed using many of the methods described herein. For the next etch step, a hard mask 308 like silicon nitride can be used to pattern on top. These 3D memories flows have an important advantage, as shown in the following: only one lithography step is required to affect multiple layers. This concept will be used in many memory flows.

“FIG. “FIG.

“FIG. 3C shows the structure 311 after SiO2 has been deposited and 314 holes have been etched for the next step of gate stack.

“FIG. The structure of the gate stack 322 after it has been formed in 3D. The gate stack could include agate dentric and agate electrode material. This could be made by CVD/ALD of first a gateoxide and then a gate material. It could also be made from metal or in-situ doped with polysilicon. Radical oxidation is another method that can be used to produce a high-quality thermal oxide. TEL SPA (slot-plan antenna) is a tool/machine that generates oxygen radicals and uses them to form thin thermal dioxides. These oxides can be formed at temperatures below 400 degrees C. It may be necessary to include a non-directional, isotropic etch step in order to create the next gate.

“FIG. 3E shows the structure 321 after stripping the dielectric 312, followed by diffusion doping to form both the drain regions 326 and the source 324 regions. The source regions 324 would connect to the source line (??SL?). The source regions 324 would be connected to the source line (?SL?). Depending on the arrangement of the array, the SL or BL can also be interchangeable. Diffusion doping converts all exposed silicon areas not covered by the gates 322 from p to n+ or n to p+ types. The transistors will be created in the small pin structure 325. The common strips 327 will serve as simple conductors acting as bit-lines and source-lines for memories that could form by the pins transistors 325.

“FIG. 3F shows the structure 331 and the extension of the bitlines 334 that could be used to create a staircase per layer access. A select gate 332 can be used to select a memory branch.

“FIG. 3G shows the structure 331 after the formation of the stair-case 336 for the bit line extension 334, and after the formation of the vertical connections to bit-lines 337 and transistor sources 338.”

“FIG. 3H shows the structure after adding the grid. This illustration can be used to structure bit-lines 356, select lines 358, sourcelines 352 or word-lines 350. The corner direction 359 illustrates the direction x,y,z. These connectivity structures allow us to select a cell so that we can choose the?x? gate lines 358. Select the?x? location. branch, the word-lines 354 choose the?y? Locate the gate in?y by choosing the word-lines 354 direction. The bit-lines 356 choose the?z? Select the drain in??z? direction. Optional select-gate lines 358 permit selection of the bank transistors along?x? direction.”

“FIG. 3I shows the structure after adding the grid with connections using an alternative structure of bit-lines and word-lines. The common gate material runs along the multiple pins. This would act as a simple conductor and word-lines.

“FIG. “FIG. Only the areas that are designated for silicification 362 are exposed, while all others are protected with photoresist and isolation oxide. Next, a metal, such as Ni Ti, Co or another known in the art material is applied to the bit lines 362. Thermal reaction can then be achieved using Rapid Thermal Anneal or laser anneal. The unreacted metal can then be etched.

“FIG. 3K is a 3D memory with a three column structure. The vertical line 338 in FIG. connects the transistors source that form the memory cell. 3G connects with the transistors source sidewall. FIG. 3K. This vertical connection could also be formed by selective epitaxy, an alternative to deposition.

“FIG. 3L shows the structure with protective covering of oxide or another protective material 366, and trench opening the sides of the memory transistors source 368. This could be a step to remove a portion of the vertical isolation between sources of stack transistors by opening the trenches 366.

“FIG. 3M shows the structure after epitaxial growth to form a vertical column connecting all sources in a stack. These columns could be silicided to improve their connectivity.

“FIG. 3N shows the structure after adding contacts 372 to the top.

FIGS. 3A-3N were created for easy understanding and drawing. People skilled in the art will understand that memory bit density can be increased using techniques used in memory design. Mirroring transistors along bit lines that are shared by right and left sides of the transistors, and mirroring across the source side to share the vertical source lines. U.S. Pat. illustrates such a structure. No. No. 8.114,757 as related to FIGS. 30A-30M and FIGS. 31A-31K.”

“FIG. 3O shows another alternative. The vertical line connecting the source side to the stack transistors 376 is shared, but the horizontal silicon bit-lines first and second bit?line 374 and 375 are not shared. The advantage to not sharing bit-lines 1 bit-line 374 or 2 bit-line 375 is that you can add silicidation, as described in FIG. 3J.”

“FIG. 3P is an alternative. The horizontal bit lines 384 of the stack transistors are shared, but not the vertical line connecting to the source side of 385 and 386 of the stack transistors are shared.”

“FIG. 4A shows a charge storage (may include a floating-body, charge trap, or other types). Memory cell of the type used for 3D RAM, as shown in FIG. 3A-3P is an enhanced version of the type used for 3D RAM, as illustrated in FIG. The memory cell could have a n-type drain 402, p-type channel 404, and a n-type source 406. In place of the single gate layer process described above, successive steps of ALD (Atomic Layer Deposition), or another type of deposition, could be used to form the tunneling oxide, charge storage layer, 414, 416, and gate 408. This memory is also known as universal memory. Each memory cell can function as both high speed volatile RAM or low power non-volatile floating gates or charge trap memories. Combining high speed RAM and low-power non-volatile back-up might be attractive for some applications. U.S. Pat. also presents a dual-use channel. No. 7,158,410 and papers by J. W. Han. titled “A Unified RAM (URAM), Cell for Multi-Functioning Capacitorless NRAM and DRAM?” Published by IEDM 2007, Dong-Il Moon et al. The title of the paper is ‘Evolution of Unified RAM: 1T DRAM and BE-SONOS Built On a Highly Scaled Vertical channel? Published at IEEE TRANSACTIONS ELECTRON DEVICES VOL. 61, NO. 1, JANUARY 2014. All of the above are incorporated herein as reference.”

“FIG. 4B shows enhancements to the FIG. 4A to the 3D memory as shown in FIG. 3A-3P.”

“FIG. 4C shows enhancements to the FIG. FIG. 4A is the 3D memory illustration. 14A-14H U.S. Patent Application No. 62/221/618, incorporated herein as a reference.”

“In U.S. Pat. No. No. 8.902,663, incorporated by reference. A select transistor is shown at the top layer of a 3D column memory cell column, as described in FIG. 8 and the associated description there. This per column select transistor could prove to be useful for many of these memory structures. This top layer select transistor can be combined with the transistors that form the memory cell beneath it by using the same lithography process. Thus, the top select transistor is at least partially aligned with the memory cells below. These select transistors can provide additional control and can be used as a buffer for the memory cells, which could improve memory access speed and aid in read and write operations. The following describes the steps involved in adding select transistors to the 3D TRAM structure. A semiconductor memory artisan would easily be able to apply this concept to any of the memory structures presented herein.

“FIG. 5A illustrates prior art 2D memory device. Memory control circuits 504 surround the memory cells 2D matrix 502 and include decoders, sense amplifiers and interfaces to external devices. Memory peripherals are the circuits 504. The memory control lines 506 run across the memory array rows and columns, miming to the peripherals circuits.

“FIG. “FIG.5” 5B shows a side view of a cross-section of a prior art 3D memory device. 3D memory, also known as 3D NAND, has recently been introduced to the market. The memory cell 3D matrix512 of such 3D-NAND is still surrounded and controlled by 514 memory control circuits. These include decoders, sense amps, interfaces with external devices and amplifiers. These memory peripheral circuits are processed in a similar manner to the 2D memory circuits built on silicon wafer substrate. These 3D memories have control lines 516 that run through the rows and columns of the memory matrix. Some control lines are built on top of 3D matrix while others are going through the bulk of the matrix. However, at the edges they are connected to 2D peripheral circuits.

“FIG. “FIG. The 3D memory matrix 522 includes columns and rows with the control circuits 524. These could still be called peripherals, but could be built on top of the matrix. In this embodiment, control lines 526 are placed underneath the peripheral circuits and in-between the memory matrix 522 and 524.

“FIG. 5D shows a side-view crosssection of alternative 3D memories made using the techniques herein. The control lines and control circuits are located underneath the memory cell matrix.

“This new type 3D memory could be constructed to gain significant advantage over prior art by using the 3D architecture illustrated in at most FIGS. 5C and 5D to divide the control lines 526 into smaller pieces. Each chunk will have its control circuits repeated. A shorter control line could reduce memory access read, write, refresh and speed up memory access time. If the stair-case is used for layer access too often, it could affect device cost. To save overhead space, proper architecture and overall memory control strategy could utilize long per-layer control lines (not illustrated). Therefore, it is important to design the memory architecture to allow for long control lines to memory within the same layers for as long as possible. Keeping the vertical control lines short and the per-layer control lines long could provide the advantages of low power and fast access for most of the time.

“As discussed with FIG. 4A, FIG. 4A, FIG. 4B, and FIG. These are non-volatile cells that use floating gate or charge trap technology. Other non-volatile memory technology options, such as M-RAM and Phase-Change or Re-RAM could also be used. Splitting the gates on one side of the memory channel could be used to control the volatile function, while the other side could be used for non-volatile functions. Splitting the gate could also be used to increase non-volatile memory density for cells with enough channel to support 2-bit per cell techniques.

“In most cases, volatile operation could interfere avec the non-volatile operations of the memory cells. It is best to not use them together and to have the unused section reset electrically to minimize interference with the used.

There are many ways that such enhanced memory can be used. These include powering down to save volatile information in the non-volatile section, and reducing sleep power by moving volatile information into non-volatile. The 3D structures shown in this figure have control circuits at the top and/or bottom for some of these uses modes. FIG. 5B and FIG. 5B and FIG. These modes could reduce the time and power needed to transfer data from volatile into non volatile portions by an order of magnitude.

“FIG. “FIG. The interface to external devices is controlled by the side memory control circuits 601. They can be used for both instruction and data input and out. These circuits 601 may include per-layer decoders. They also control the internal memory blocks. This could reduce the stair-case overhead. Each block 602 is a sub-memory with its own top peripherals circuits that control most of the control lines. This design allows data to be moved from one section to another in parallel. These operations could be synchronized by the side memory control circuits 601 so that they can be performed one layer at a.m.

“FIG. 6B shows the block diagram for a peripherals circuit in a block 602. This block diagram 604 could show you the block diagram of a unit block control circuit.

“Central controller 630 commands and controls these operations for sleep mode, recovery mode, etc.”

“In-Out interface controller to interface data and with device controller 601”

“Sense Amplifiers620 are used to sense data from a memory cell according the mode of operation, and to convert side-memory control circuits 601 into a digital bit that could be temporarily stored within the unit memory cash 634.”

“Signal generators 618 are used to generate the voltages and currents required for proper read/write of memory cells. These circuitry, including charge pumps, can be shared among all units and placed in side memory control circuits 601.

Blocks 612-614, 616 and 617 are for various control lines like bit-lines or word-lines. The 616 layer decoders could be removed from unit 604 and placed in the general per-layer circuits at the side memory control circuits 601.

This memory architecture has the added advantage of allowing you to access large blocks of data simultaneously, as many blocks 602 can be accessed at once. To maximize array efficiency, only one per-layer staircase should be used. This would limit parallel action to one layer. This could be controlled by proper system data structure.

“This 3D Memory could also include redundancy circuitry that allows for repair and replacement of memory bits. FIG. FIG. 5D could be used to access substantially all memory control lines on both sides?top and bottom, and to duplicate the device control circuit 524 at bottom. This redundancy scheme could be reduced to the level of memory block control units 602. If one unit block control circuit is defective, it can be replaced with a compatible one at the opposite end. As an alternative, each unit block control circuitry can be constructed with two stratums. One is a backup for the other.

“The memory control redundancy could apply to any of these 3D memories.”

FIGS. 7-13 show another embodiment of monolithic, 3D memory according the present invention. FIGS. 7-13 are outlined below. Mono-crystalline transistors are used. The channels of mono-crystalline transistors run vertically so that current flows vertically across the device’s layers, rather than horizontally. This structure is low-cost because it uses the same lithography, deposition, and etch techniques as multiple layers to form self-aligned, vertically oriented transistors.

“FIG. 7A shows the starting material structure of these vertically oriented 3D memories. It contains interchanging layers of designated source/drain material 702 and designated channel material 704. These layers can be processed epitaxially using in-situ alternating P/P+ to N/N+ doping or between SiGe and alternating silicon layers, etc. You may consider using a high-etch selectivity process to etch adjacent layers faster than the (S/D), layers 702. This will allow for a more efficient composition of these layers. These layers can be as thin as a few nm to hundreds of millimeters thick. Dopant diffusion suppression may also be achieved by low-temperature epitaxial processes such the AMAT 450-500 degrees C. epi process. Interlayer diffusion barriers can also be used, for example, a thin, single, or double atomic layer of an anti-diffusion suppressor like carbon.

“For instance, the composition of the S/D layer 702 could be N+ silica while the channel layer 704 could contain P type silicon. The selective etch process would use anodic etching described in U.S. Pat. No. No. 8,470,689 as described herein.

“An alternative to using P++ silicon is to use S/D layers 702 & N silicon channel layers 704; the later selective etch would be performed with the NH4OH solution, as suggested by Golod et al.”

“Yet another option is to use N+ silica for (S/D), layers 702 and 704, and P type SiGe channel layers 704, and the later selectiveetch would utilize the process described by Se Hwan Park and colleagues in a piper entitled?Novel (3D) NAND flash memory array having tied bit-line and ground select transistor (TiGer). Published in TECHNICAL RELEASE OF IEICE 711 (APWF_PSH), a paper written by F L W. Fathauer et all titled ‘New class of Si-based Superlattices: Alternating Layers of Crystal Si and Porous Amorphous Si, ?, Ge, Alloys? Published by Appl. Phys. Lett. Lett. Published at IEEE TRANSACTIONS ELECTRON DEVICES VOL. 58, NO. 4, APRIL 2011, and U.S. Pat. No. No. 8,501,609 are all incorporated herein as reference.”

“For simplicity, we will outline the flow of a vertical channel 3D structure memory including S/D layers 702 and N+ silicon as well as channel layers 704. Any person skilled in the arts would be able modify the flow to accommodate other embodiments.

“On top the multilayer of alternating 702/704 is deposited a hard mask material 706.

“FIG. 7B shows how etching the structure to create multilayer ridges 709, and valleys 708 between them resulted in repeating-ridges structure 707. The valleys and ridges can be as wide as 10 nm, or lower than that to hundreds of nm. A good choice at the moment is 50 nm. Consider the thickness of layers 702/704, type of memory built, and other factors when determining the width of the valleys and ridges. A similar width and thickness might be possible.”

“FIG. 7C shows the structure after selective isotropic etching of channel layers 704 to form horizontal notches 719, while leaving the S/D layers 710 untouched. You can use a selective plasma etch. You can increase the selectivity by first creating pores in the desired areas of the channel layers using selective anodization. This would allow plasma etch to be extremely selective. Warm KOH can also be used to selectively etch the crystallographic planes 100>.

“FIG. 7D shows the structure after depositing a stack tunneling oxide/charge trap/control oxide layers 712 such as oxide/nitride/oxide or gate conductive material 714. This step can be performed by Atomic Layer Deposition or other processes for fabricating semiconductor devices. To remove substantial amounts of gate material from the sides of the S/D 713 layers, a directional anisotropic step could be used. Stringers can also be removed by a slight touch-up isotropicetch.

“FIG. 7E shows the structure after filling in the trenches 708 (FIG. 7B is filled with insulating material 716. An etch step then forms vertical gaps 710 along the ridges 709 of FIG. 7B to create vertical strings 722 from alternating N+/P materials. Two steps could be used to etch the stack of multilayers of alternating 702/704 to form vertical strings 722. Anisotropic etch first the stack of multilayers of alternating 702/704 in order to form the vertical individual string 722. Then, isotropic selectively etch to remove source/drain 702 between the gate stack 712. While leaving the horizontal going gates and oxide lines. To serve as a common ground, the etching can be stopped prior to the lowest N+ layer. You may also use conductive etch-stop layers.

“FIG. 7F shows a vertical cross-sectional view of FIG. 7E. 7E. The common ground line could be the remaining bottom material 738. Ground select gate could be the lower gate line 740. The string drain area would be located at the top of the strings 732 and could be connected to the bit-lines later. This structure creates a matrix of vertically-oriented non-volatile NAND memories cells. Horizontal control gates 742 are the memory word lines that control current through the vertical channels. They may also form vertical NAND strings.

“FIG. 7G shows a vertical cross-section of one vertical NAND string 736 perpendicularly to the direction of the metal-gate-word-line.

“FIG. 7H shows the 3D NAND structure after adding the grid memory control lines: word, bit, string, select-lines 767 and ground select-lines 751.

“In this 3D structure of memory, as well as in all other memory structures, the horizontal per-layer line through the matrix could limit the power performance of a device in terms of how long it can be made. To save silicon real-estate, and to reduce costs per bit, the lines required for the interconnect structure of the stair-cases must be longer. This stair-case could be placed on either side of the line, which can help to reduce cell to cell variation and improve power and delay. Splitting the device into multiple blocks can improve real estate efficiency by sharing each staircase between the right and left sides of each block.

“FIG. 8A shows a structure that can be used to form a NOR 3D memory. It begins with FIG. 20B of the U.S. Patent Application 62/221 618. To form the charge storage stack 802, first elongated strips are formed using etching and masking techniques. These strips are coated with a dielectric multilayer tunneling-oxide, charge-trap, and control gate oxide layers. A gate 804 material, such as tungsten (W), or polysilicon, is deposited on top. The charge storage stack 802 or gate overcoat 804 are patterned using masking and etching techniques in order to form second elongated stripes perpendicularly to said first elongated strip. ALD techniques could be used for the deposition step.

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