IMEC zvw (Leuven, BE)

The disclosed technology generally relates to semiconductor devices as well as methods of forming the same. One aspect of the technology disclosed is a method of making a vertical field-effect transistor (FET). It involves the creation of a plurality semiconductor structures protruding from the lower source/drain layer of the substrate. It is possible to arrange the semiconductor structures into an array of rows and columns. The method may involve etching metal line trenches between at least a portion of the rows and creating metal lines inside the trenches of metal to contact the lower source/drain layer. This technique may also involve the creation of gate structures which partially enclose channels of semiconductor structure above the lower source/drain layers and the creation of higher source/drain metallic contacts on the semiconductor structure’s upper source/drain layer that is located above these channel sections.

Technical Field

The technology disclosed generally refers to semiconductor devices , and specifically, to methods for manufacturing semiconductor devices like field-effect transistors (FET).

Description of the related Technology

To offer greater power- and area-efficiency circuit designs new transistor designs are being designed. One form of non-planar field effect transistor (FET) device is the vertical channel FET device.

Vertical channel FET devices (also called VFET devices) include the vertical nanowireor nanosheet-FET (vertical NWFET or NSFET) having gates that are at least partially or entirely, that covers an element of the channel of a vertically oriented nanowireor the nanosheet semiconductor structure.

Due to their vertically oriented channel designs, VFET devices’ gate length may not be affected by linewidth, but rather by the vertical dimension of the gate electrode. Additionally the source and drain parts of avertical transistor device are vertically offset in relation to each other. VFET devices are able to be constructed in large, efficient arrays for these reasons.

Contacting the source/drains is required to create functional circuits. However because of the orientation of the channel structures as well as the vertical displacement of source and drains, connecting the sources below (or drains as the situation is) can be more challenging than the contacting of horizontal channel devices. For VFETs, contact may be based on the provision of vias that are vertical to each source or drain. To permit connections with low resistance, however the vertical vias have to have a minimum cross-section. This can make it challenging to incorporate into the dense arrays.

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