Inventors and Patents From the City of Sunnyvale

The city of Sunnyvale has a rich history of innovation and invention. In the past decade, it has produced more than ten U.S. patents, including one that covers a computer chip’s architecture. One recent patent was issued to Fisker Automotive, Irvine, Calif., while another was awarded to NVIDIA, Santa Clara, Calif., for an integrated body memory on SOI with logic transistors on a bulk substrate.

Fisker Automotive, Irvine, Calif., has been assigned a patent

Fisker Automotive is an electric vehicle manufacturer based in Irvine, California. It was established in 2002. The company is owned by David Morgenstern, who lives in Palo Alto, Calif. The company has a patent for a battery-powered electric vehicle. The patent was filed on Oct. 8, 2008, and covers battery technology and electric vehicle powertrains.

Fisker Automotive has been assigned a patent from the City Of Sunnyvale for its concept vehicle. The company began its life as Fisker Coachbuild, a company that tried to revive coach-building automobiles. The company produced the Tramonto and Latigo on Mercedes-Benz SL or BMW 6 Series chassis, and sold several cars. The company then restructured itself as Fisker Automotive.

The DOE loan to Fisker Automotive represents two percent of the $25 billion Advanced Technologies Manufacturing Loan Program, a program that Congress passed in November 2008. The DOE is aiming to support the development of energy-efficient and advanced-technology vehicles. Fisker Automotive is a company that has already supported hundreds of American jobs with private funding and will help put the United States on the forefront of the auto industry in the future.

The company is now looking for a manufacturing plant to build the Karma. It needs to produce around 15,000 Karmas per year. The company plans to build the next generation of the car in the U.S. and also has plans to export the cars.

Other California companies have filed patent applications for their electric vehicles. One of the newest was Integrated Vascular Systems, which was awarded a patent on Dec. 21. Its patent application, No. 7,881,031 (Sunnyvale), was filed on Nov. 4, 2005 (12/264,751) by two Germans.

Intel, Santa Clara, Calif., has been assigned a patent for an embedded power gating

The patent describes a technique for controlling the power consumption of two or more processing cores independently. One embodiment of the technique places a processing core in a c3 state, where it is idle. This enables a processor to conserve power while running a number of logical processes.

The technology can be used in a variety of applications, including desktop PCs and servers. Intel has been assigned patents related to computer architecture and power efficiency. The patents cover a wide variety of microprocessor products, such as the Pentium III, Pentium 4, and Pentium M. The company also has a product line of chips called the Core.

The patent also relates to a method of adjusting a performance resource for power management requests. This technique may include checking the current operating power state of logical processors and adjusting the performance resource based on previous power management commands.

The patents assigned to Intel and NVIDIA include the right to use, sell, offer for sale, and dispose of the product worldwide. NVIDIA and Intel will not have to pay third-party licensing fees for this patent, which demonstrates that NVIDIA and Intel are collaborating in a mutually beneficial way.

The patent also enables the use of power control logic to adjust the power state of each core on a chip. This power control logic is capable of responding to activity levels in each core and adjusting the voltage and clocks accordingly. This may allow for a more efficient power management system.

One embodiment of the patented invention is a microprocessor system that includes a first logical processor 310, a second logical processor 620, and a controller hub 630. These elements may include a single integrated circuit or a number of integrated circuits. The controller hub 630 may include a first integrated circuit that interfaces with the system memory.

Another aspect of the technology is the ability to control the power consumption of processing components according to their specification. For example, the operating system may place a processing core in a “c3” state, which lowers the operating voltage without changing output data. This method can be used in subnotebooks, silent desktops, and blade servers.

The patented invention uses power control logic that is embedded in the processor. The power control logic may be triggered by a change in work load or activity level. It may also include a clock gating mechanism.

The patented invention uses a multi-threading architecture, in which multiple threads share common processor resources, including caches, branch predictors, and bus interfaces. It may also include the use of multiple architectural states, which can include a combination of L1 and L2 cache.

Intel has been assigned a patent for an integrated body memory on SOI with logic transistors on bulk substrate

An integrated body memory on SOI with logic transistor on bulk substrate was invented by Intel and six co-inventors. The patent application (7,882,284) was filed on Sept. 29, 2005. The inventors include John Shen of San Jose, Calif., and Mark L. Doczy of Beaverton, Ore., among others.

SOI is a method to integrate multiple integrated circuits, thereby improving performance and chip yields. The technology allows designers to design the logic in different strata of a single silicon wafer, with different types of metal interconnect layers and supply voltages.

Logic transistors on SOI are the most commonly used type of memory for mobile devices. These chips are extremely fast and can be stacked in any configuration. A high-density SOI memory is also known as a CMOS memory.

In the space shuttle, the microelectronic circuits are designed for radiation-tolerant environments. For example, the circuits used in the space shuttle utilize RHBD MOSFETs. So, it is possible to design such a memory chip using a low-power process.

A high V GB value is needed to generate negative charge carriers in the inversion layer. This inversion layer is located in a thin layer right next to the interface. As the voltage increases, the transistor’s drain voltage also increases exponentially. This subthreshold current is sometimes referred to as weak-inversion leakage.

A patent application for a hybrid system based on SOI technology has also been issued. This design incorporates logic transistors on SOI. It also includes an implant delivery system. In addition to this, the EACC chip is also covered by a patent application filed by Glaukos Therapeutics, Inc. on Aug. 17, 2007.

Another patent has been assigned to Fluor Technologies. The patented technology includes an integrated body memory on SOI with logic semiconductors. The company received the patent on Nov. 4, 2007 (12/264,751) from two inventors.

The process of assembling an integrated body memory on SOI with logic semiconductors on bulk substrate includes a thin layer of silicon dioxide between a group III-V substrate and a high-k gate dielectric layer. The thin layer acts as a transition layer between the bulk substrate and high-k gate dielectric layer.

Reducing the size of transistors has helped to advance the technology. A computer’s computing power depends on the number of operations per second and the size of the data it processes. By shrinking transistor sizes, more transistors can be fit into a chip. Furthermore, smaller transistors use lower voltages, enabling them to operate at a lower voltage. They also have a lower output resistance.

The Forksheet transistor design is similar to RibbonFETs, but it uses N and P channels together. The new design has two advantages: reduced energy consumption and a reduced footprint.